TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 245

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

10.4.9
31-8
7-5
4
3
2
1
0
After reset
After reset
After reset
After reset
bit symbol
bit symbol
bit symbol
bit symbol
Bit
-
-
RFST
TFIE
RFIE
RXTXCNT
CNFG
Note 1: Regarding TX FIFO, the maximum number of bytes being configured is always available. The available num-
Note 2: The FIFO can not use in 9bit UART mode.
Bit Symbol
SCxFCNF ( FIFO Configuration Register)
31
23
15
0
0
0
7
0
-
-
-
-
ber of bytes is the bytes already written to the TX FIFO.
R
R/W
R/W
R/W
R/W
R/W
R/W
Type
30
22
14
0
0
0
6
0
Read as 0
Be sure to write "000"
Bytes used in RX FIFO
0:Maximum
1:Same as FILL level of RX FIFO
When RX FIFO is enabled, the number of RX FIFO bytes to be used is selected (Note1)
0: The maximun number of bytes of the FIFO configured (see also <CNFG>).
1: Same as the fill level for receive interrupt generation specified by SCxRFC <RIL[1:0]>
TX interrupt for TX FIFO
0: Disabled
1:Enabled
When TX FIFO is enabled, transmit interrupts are enabled or disabled by this parameter.
RX interrupt for RX FIFO
0: Disabled
1:Enabled
When RX FIFO is enabled, receive interrupts are enabled or disabled by this parameter.
Automatic disable of RXE/TXE
0: None
1: Auto diabled
Controls automatic disabling of transmission and reception.
Setting "1" enables to operate as follows
Enables FIFO.
0: Disabled
1: Enabled
If enabled, the SCxMOD1 <FDPX[1:0]> setting automatically configures FIFO as follows:
(The type of TX/RX can be specified in the mode control register 1 SCxMOD1<FDPX[1:0]>).
-
-
-
-
Half duplex RX
Half duplex RX
Half duplex TX
Half duplex TX
Full duplex
Full duplex
29
21
13
0
0
0
5
0
-
-
-
-
When receive shift register, the receive buffer and the RX FIFO are filled,
SCxMOD0<RXE> is automatically set to "0" to inhibit further reception.
When the TX FIFO, the transmit buffer and the transmit shift register is empty,
SCxMOD1<TXE> is automatically set to "0" to inhibit further transmission.
When either of the above two conditions is satisfied, TXE/RXE are automatically
set to "0" to inhibit further transmission and reception.
RX FIFO 4byte
TX FIFO 4byte
RX FIFO 2byte + TX FIFO 2byte
Page 225
RFST
28
20
12
0
0
0
4
0
-
-
-
TFIE
27
19
11
Function
0
0
0
3
0
-
-
-
RFIE
26
18
10
0
0
0
2
0
-
-
-
TMPM330FDFG/FYFG/FWFG
RXTXCNT
25
17
0
0
9
0
1
0
-
-
-
CNFG
24
16
0
0
8
0
0
0
-
-
-