TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 354

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

12.4
Operations
<CECACKDIS>
CECRCR1
Transmission
Reception
(6)
proximately 1.526 ms. The start time of outputting "Low" is specified with CECRCR1<CECLNC> bit
that sets the noise cancelling time.
error, buffer overrun and waveform error) is suspended or not. Setting "1" generates no interrupt at the
error detection.
bits are interrupted, it is determined as a timeout, based on the setting in <CECTOUT> of the CECRCR1
register.
The following describes the ACK response timing.
When the falling edge of the ACK bit from the initiator is detected, this IP outputs "Low" for ap-
Configure the CECRCR1 <CECRIHLD> bit to specify if a receive error interrupt (maximum cycle
If data continues to the ACK bit, an ACK response is executed by a reversed logic. If the subsequent
After the ACK response or the timeout determination, an interrupt is generated.
Note:<CECLNC> must be used under the same setting as CECTCR<CECDTRS>.
Receive Error Interrupt Suspend
Register setting
(not responding logical "0")
(responding logical "0")
(0ms to approx. 0.092ms)
"0"
"1"
<CECLNC>
0/fs - 3/fs
0.6±0.2 ms
Conformity
Yes
Page 334
Header block address
(approx.1.526ms)
50/fs
Discrepancy
No
Conformity
Yes
No
TMPM330FDFG/FYFG/FWFG
Data block address
Discrepancy
No
No