TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 340

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

12.3
Registers
7
6-4
3-2
1
0
Bit
−
CECDAT[2:0]
CECTOUT[1:0]
CECRIHLD
CECOTH
Note 1: The settings in <CECHNC>, <CECLNC> and <CECDAT> are also used in receiving an ACK response at transmis-
Note 2: Changing the configurations during transmission or reception may harm its proper operation. Before the change, set
Note 3: A broadcast message is received regardless of the <CECOTH> register setting.
Note 4: <CECLNC> must be used under the same setting as CECTCR<CECDTRS>.
Bit Symbol
sion.
the CECREN <CECREN> bit to disable the reception and read the <CECREN> bit and the CECTEN <CECTRANS>
bit to ensure that the operation is stopped.
R
R/W
R/W
R/W
R/W
Type
Specifies the maximum time to identify as a valid bit.
Base time is 90/fs (approx.2.747 ms). Enables to specify it between the ranges −4/fs to +3/fs by the unit of 1/
fs.
An interrupt is generated when one bit cycle is longer than the specified time.
Read as 0.
Point of determining the data as 0 or 1.
Specifies the point of determining the data as logical "0" or logical "1".
Base time is 34/fs (approx.1.038 ms). Enables to specify it within ±6/fs by the unit of 2/fs.
Cycle to identify timeout
Specifies the time to determine a timeout. Enables to specify it between 1 bit and 3 bits for each bit cycle.
This setting is used to detect a timeout occurs when the <CECRIHLD> bit is valid.
Error interrupt suspend
0: Not suspended
1: Suspended
Specifies if a receive error interrupt (maximum cycle error, buffer overrun and waveform error) is suspended
or not.
Setting "1" generates no interrupt at the error detection. If data continues to an ACK bit, an ACK response is
executed by a reversed logic. If the subsequent bits are interrupted, it is determined as a timeout, based on
the setting in <CECTOUT>.
After the ACK response or the timeout determination, an interrupt is generated.
Data reception at logical address discrepancy
0: Not received
1: Received
Specifies if data is received or not when destination address does not correspond with the address set in the
CECADD register.
000:
001:
010:
011:
00:
01:
10:
11:
34/fs (approx. 1.038ms)
34/fs + 2/fs
34/fs + 4/fs
34/fs + 6/fs
1 bit cycle
2 bit cycle
3 bit cycle
Reserved
Page 320
Function
100:
101:
110:
111:
34/fs − 2/fs
34/fs − 4/fs
34/fs − 6/fs
Reserved
TMPM330FDFG/FYFG/FWFG