TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 241

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

10.4.7
31-8
7
6
5
4
3
After reset
After reset
After reset
After reset
bit symbol
bit symbol
bit symbol
bit symbol
Bit
−
TBEMP
RBFLL
TXRUN
SBLEN
DRCHG
Bit Symbol
SCxMOD2 (Mode Control Register 2)
TBEMP
31
23
15
0
0
0
7
1
-
-
-
R
R
R
R
R/W
R/W
Type
RBFLL
30
22
14
0
0
0
6
0
Read as 0.
Transmit buffer empty flag.
0: Full
1: Empty
If double buffering is disabled, this flag is insignificant.
This flag shows that the transmit double buffers are empty. When data in the transmit double buffers is moved
to the transmit shift register and the double buffers are empty, this bit is set to "1".
Writing data again to the double buffers sets this bit to "0".
Receive buffer full flag.
0: Empty
1: Full
This is a flag to show that the receive double buffers are full.
When a receive operation is completed and received data is moved from the receive shift register to the receive
double buffers, this bit changes to "1" while reading this bit changes it to "0".
If double buffering is disabled, this flag is insignificant.
In transmission flag
0: Stop
1: Operate
This is a status flag to show that data transmission is in progress.
<TXRUN> and <TBEMP> bits indicate the following status.
STOP bit (for UART)
0 : 1-bit
1 : 2-bit
This specifies the length of transmission stop bit in the UART mode.
On the receive side, the decision is made using only a single bit regardless of the <SBLEN> setting.
Setting transfer direction
0: LSB first
1: MSB first
Specifies the direction of data transfer in the I/O interface mode.
In the UART mode, set this bit to LSB first.
-
-
-
<TXRUN>
1
0
TXRUN
29
21
13
0
0
0
5
0
-
-
-
<TBEMP>
Page 221
−
1
0
SBLEN
28
20
12
0
0
0
4
0
-
-
-
Transmission in progress
Transmission completed
Wait state with data in Transmitt buffer
DRCHG
27
19
11
Function
0
0
0
3
0
-
-
-
Status
WBUF
26
18
10
0
0
0
2
0
-
-
-
TMPM330FDFG/FYFG/FWFG
25
17
0
0
9
0
1
0
-
-
-
SWRST
24
16
0
0
8
0
0
0
-
-
-