TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 279

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

Transmit data
write timing
SCLK0 input
(<SCLKS>=0
Rising edge mode)
SCLK0 input
(<SCLKS>=1
Falling edge mode)
TXD0
(INTTX0 interrupt
request)
Transmit data
write timing
SCLK0 input
(<SCLKS>=0
Rising edge mode)
SCLK0 input
(<SCLKS>=1
Falling edge mode)
TXD0
(INTTX0 interrupt
request)
TBEMP
Transmit data
write timing
SCLK0 input
(<SCLKS>=0
Rising edge mode)
SCLK0 input
(<SCLKS>=1
Falling edge mode)
TXD0
(INTTX0 interrupt
request)
TBEMP
PERR
(Functions to detect
under-run errors)
Figure 10-13 Transmit Operation in the I/O Interface Mode (SCLK Input Mode)
bit 0
<WBUF> = "1" (if double buffering is enabled and there is no data in buffer2)
bit 0
bit 0
<WBUF> = "1" (if double buffering is enabled and there is data in buffer2)
bit 1
bit 1
bit 1
<WBUF> = "0" (if double buffering is disabled)
Page 259
bit 5
bit 5
bit 5
bit 6
bit 6
bit 6
bit 7
bit 7
bit 7
TMPM330FDFG/FYFG/FWFG
A
A
A
bit 0
bit 0
1
bit 1
bit 1
1