TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 306

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

11.5
Control in the I2C Bus Mode
SCL (Line)
Internal SDA output (masterA)
Internal SDA output(master B)
SDA Line
Figure 11-8 Example of Master B Lost Arbitration (D7A = D7B, D6A = D6B)
When the SCL line goes high at the point b, the slave device reads the SDA line data, i.e., data transmitted by
Master A. At this time, data transmitted by Master B becomes invalid.
the data transfer initiated by another master. If two or more masters have transmitted exactly the same first data
word, the arbitration procedure continues with the second data word.
there is a difference between these two values, Arbitration Lost occurs and SBIxSR<AL> is set to "1".
receiver.Therefore, the serial bus interface circuit stops the clock output during data transfer after <AL> is set to
"1".
Then Master A pulls the SDA bus line to the "Low" level because the line has the wired-AND connection.
This condition of Master B is called "Arbitration Lost". Master B releases its SDA pin, so that it does not affect
A master compares the SDA bus line level and the internal SDA output level at the rising of the SCL line. If
When <AL> is set to "1", SBIxSR<MST, TRX> are cleared to "0", causing the SBI to operate as a slave
<AL> is cleared to "0" when data is written to or read from SBIxDBR or data is written to SBIxCR2.
Access to SBIxDBR or
SBIxCR2
MasterA
MasterB
<AL>
<MST>
<TRX>
Internal SCL
Internal SDA
Internal SCL
InternalSDA
output
output
output
output
D7A D6A
D7B D6B
1
1
Figure 11-7 Lost Arbitration
2
2
D5A D4A
3
3
Internal SDA output is fixed to "High"level .
due to Arbitration Lost of Master B.
4
4
Page 286
D3A D2A D1A
5
Clock output dstops here
a
6
b
7
Loses arbitration and sets the
internal SDA output to “1”.
D0A
8
9
TMPM330FDFG/FYFG/FWFG
D7A'
1
D6A'
2
D5A' D4A'
3
4