TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 311

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

SCLx pin
SDAx pin
<PIN>
INTSBIx
interrupt
request
SCLx pin
Write to SBIxDBR
SDAx pin
<PIN>
INTSBIx
interrupt request
(2)
Figure 11-10 <BC[2:0]>= "000",<ACK>= "1" (Transmitter Mode)
Figure 11-11 <BC[2:0]>= "000",<ACK>= "1" (Receiver Mode)
from SBIxDBR to release the SCL line. (The data read immediately after transmission of a slave address
is undefined.)On reading the data, <PIN> is set to "1", and the serial clock is output to the SCL pin to
transfer the next data word.In the last bit, when the acknowledgment signal becomes the "Low" level,
"0" is output to the SDA pin.
pin to the "Low" level.Each time the received data is read from SBIxDBR, one-word transfer clock and
an acknowledgement signal are output.
before reading the data word second to last.
[2:0]> must be set to "001" and the data must be read so that a clock is generated for 1-bit transfer.
transfer to the transmitter as an acknowledgment signal.
If the next data to be transmitted has eight bits, the transmit data is written into SBIxDBR.
If the data has different length, <BC[2:0]> and <ACK> are programmed and the received data is read
After that, the INTSBIx interrupt request is generated, and <PIN> is cleared to "0", pulling the SCL
To terminate the data transmission from the transmitter, <ACK> must be cleared to "0" immediately
This disables generation of an acknowledgment clock for the last data word.
When the transfer is completed, an interrupt request is generated. After the interrupt processing, <BC
At this time, the master receiver holds the SDA bus line at the "High" level, which signals the end of
Receiver mode (<TRX> = "0")
Read the received data
D7
1
D7
1
D6
2
D6
2
D5
3
D5
3
D4
4
D4
Page 291
4
D3
5
D3
5
D2
6
D2
6
D1
7
D1
7
D0
8
D0
TMPM330FDFG/FYFG/FWFG
8
ACK
9
Master output
Slave output
ACK
9
Acknowledgment signal
Master output
Slave output
Next D7
Acknowledgement
from receiver
to transmitter