AD9883AKSTZ-140 Analog Devices Inc, AD9883AKSTZ-140 Datasheet - Page 15

• Manufacturer Part Number: AD9883AKSTZ-140
• Description: IC FLAT PANEL INTERFACE 80-LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9883AKSTZ-140

• Applications: Displays, Monitors, TV
• Interface: Analog
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 80-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2-Wire Serial Register Map
The AD9883A is initialized and controlled by a set of registers,
which determine the operating modes. An external controller is
REV. B
Hex
Address
00H
01H*
02H*
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
Write and
Read or
Read Only
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits
7:0
7:0
7:4
7:3
7:3
7:0
7:0
7:0
7:0
7:0
7:0
7:1
7:1
7:1
7:0
Default
Value
01101001
1101****
01******
**001***
10000***
10000000
10000000
00100000
10000000
10000000
10000000
1000000
1000000
1000000
0*******
*1******
**0*****
***0****
****0***
*****0**
******0*
*******0
*
*
*
Register
Name
Chip Revision
PLL Div MSB This register is for Bits [11:4] of the PLL divider. Greater values mean
PLL Div LSB
Phase Adjust
Clamp
Placement
Clamp
Duration
Hsync Output
Pulsewidth
Red Gain
Green Gain
Blue Gain
Red Offset
Green Offset
Blue Offset
Sync Control
Table VI. Control Register Map
–15–
Sets the number of pixel clocks that HSOUT will remain active.
Controls ADC input range (contrast) of each respective channel.
Function
An 8-bit register that represents the silicon revision level.
Revision 0 = 0000 0000.
the PLL operates at a faster rate. This register should be loaded first
whenever a change is needed. This will give the PLL more time to lock.
Bits [7:4] of this word are written to the LSBs [3:0] of the
PLL divider word.
Bits [7:6] VCO Range. Selects VCO frequency range.
(See PLL description.)
Bits [5:3] Charge Pump Current. Varies the current that drives the
low-pass filter. (See PLL description.)
ADC Clock Phase Adjustment. Larger values mean more delay.
(1 LSB = T/32)
Places the Clamp signal an integer number of clock periods after the trail-
ing edge of the Hsync signal.
Number of clock periods that the Clamp signal is actively clamping.
Greater values give less contrast.
Controls dc offset (brightness) of each respective channel. Greater
values decrease brightness.
Bit 7 – Hsync Polarity Override. (Logic 0 = Polarity determined by
chip, Logic 1 = Polarity set by Bit 6 in register 0EH.)
Bit 6 – Hsync Input Polarity. Indicates polarity of incoming Hsync
signal to the PLL. (Logic 0 = Active Low, Logic 1 = Active High.)
Bit 5 – Hsync Output Polarity. (Logic 0 = Logic High Sync,
Logic 1 = Logic Low Sync.)
Bit 4 – Active Hsync Override. If set to Logic 1, the user can select
the Hsync to be used via Bit 3. If set to Logic 0, the active interface
is selected via Bit 6 in register 14H.
Bit 3 – Active Hsync Select. Logic 0 selects Hsync as the active
sync. Logic 1 selects Sync-on-Green as the active sync. Note that the
indicated Hsync will be used only if Bit 4 is set to Logic 1 or if both
syncs are active. (Bits 1, 7 = Logic 1 in register 14H.)
Bit 2 – Vsync Output Invert. (Logic 1 = No Invert, Logic 0 = Invert.)
Bit 1 – Active Vsync Override. If set to Logic 1, the user can select
the Vsync to be used via Bit 0. If set to Logic 0, the active interface
is selected via Bit 3 in register 14H.
Bit 0 – Active Vsync Select. Logic 0 selects Raw Vsync as the output
Vsync. Logic 1 selects Sync Separated Vsync as the output Vsync.
Note that the indicated
employed to write and read the control registers through the
two-line serial interface port.
Vsync will be used only if Bit 1 is set to Logic 1.
AD9883A