AD9883AKSTZ-140 Analog Devices Inc, AD9883AKSTZ-140 Datasheet - Page 16

• Manufacturer Part Number: AD9883AKSTZ-140
• Description: IC FLAT PANEL INTERFACE 80-LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9883AKSTZ-140

• Applications: Displays, Monitors, TV
• Interface: Analog
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 80-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9883A
Hex
Address
0FH
10H
11H
12H
13H
14H
15H
Write and
Read or
Read Only
R/W
R/W
R/W
R/W
R/W
RO
R/W
Bits
7:1
7:3
7:0
7:0
7:0
7:0
7:0
Default
0*******
10111***
00100000
00000000
00000000
1111****
Value
*1******
**0*****
***0****
****1***
*****1**
******1*
*****0**
******0*
*******0
****1***
*****1**
******1*
*******1
Table VI. Control Register Map (continued)
Register
Name
Sync-on-Green
Threshold
Sync Separator
Threshold
Pre-Coast
Post-Coast
Sync Detect
Test Register
–16–
Function
Bit 7 – Clamp Function. Chooses between Hsync for Clamp
signal or another external signal to be used for clamping.
(Logic 0 = Hsync, Logic 1 = Clamp.)
Bit 6 – Clamp Polarity. Valid only with external Clamp signal.
(Logic 0 = Active High, Logic 1 Selects Active Low.)
Bit 5 – Coast Select. Logic 0 selects the coast input pins to be
used for the PLL coast. Logic 1 selects Vsync to be used for the
PLL coast.
Bit 4 – Coast Polarity Override. (Logic 0 = Polarity determined by
chip, Logic 1 = Polarity set by Bit 3 in register 0FH.)
Bit 3 – Coast Polarity. Selects polarity of external Coast signal.
(Logic 0 = Active Low, Logic 1 = Active High.)
Bit 2 – Seek Mode Override. (Logic 1 = Allow Low Power Mode,
Logic 0 = Disallow Low Power Mode.)
Bit 1 – PWRDN. Full Chip Power-Down, Active Low. (Logic 0 =
Full Chip Power-Down, Logic 1 = Normal.)
Sync-on-Green Threshold. Sets the voltage level of the Sync-on-
Green slicer’s comparator.
Bit 2 – Red Clamp Select. Logic 0 selects clamp to ground.
Logic 1 selects clamp to midscale (voltage at Pin 37).
Bit 1 – Green Clamp Select. Logic 0 selects clamp to ground.
Logic 1 selects clamp to midscale (voltage at Pin 37).
Bit 0 – Blue Clamp Select. Logic 0 selects clamp to ground.
Logic 1 selects clamp to midscale (voltage at Pin 37).
Sync Separator Threshold. Sets how many internal 5 MHz clock
periods the sync separator will count to before toggling high or low.
This should be set to some number greater than the maximum
Hsync or equalization pulsewidth.
Pre-Coast. Sets the number of Hsync periods that Coast becomes
active prior to Vsync.
Post-Coast. Sets the number of Hsync periods that Coast stays
active following Vsync.
Bit 7 – Hsync detect. It is set to Logic 1 if Hsync is present on the
analog interface; otherwise it is set to Logic 0.
Bit 6 – AHS: Active Hsync. This bit indicates which analog Hsync
is being used. (Logic 0 = Hsync Input Pin, Logic 1 = Hsync from
Sync-on-Green.)
Bit 5 – Input Hsync Polarity Detect. (Logic 0 = Active Low,
Logic 1 = Active High.)
Bit 4 – Vsync Detect. It is set to Logic 1 if Vsync is present on the
analog interface; otherwise it is set to Logic 0.
Bit 3 – AVS: Active Vsync. This bit indicates which analog Vsync
is being used. (Logic 0 = Vsync Input Pin, Logic 1 = Vsync from
Sync Separator.)
Bit 2 – Output Vsync Polarity Detect. (Logic 0 = Active Low,
Logic 1 = Active High.)
Bit 1 – Sync-on-Green Detect. It is set to Logic 1 if sync is present
on the Green video input; otherwise it is set to 0.
Bit 0 – Input Coast Polarity Detect. (Logic 0 = Active Low, Logic 1 =
Active High.)
Bits [7:4] Reserved for future use.
Bit 3 – Must be set to 1 for proper operation.
Bit 2 – Must be set to 1 for proper operation.
Bit 1 – 4:2:2 Output Formatting Mode (Logic 0 = 4:2:2 mode, Logic 1=
4:4:4 mode)
Bit 0 – Must be set to 0 for proper operation.
REV. B