AD9883AKSTZ-140 Analog Devices Inc, AD9883AKSTZ-140 Datasheet - Page 19

• Manufacturer Part Number: AD9883AKSTZ-140
• Description: IC FLAT PANEL INTERFACE 80-LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9883AKSTZ-140

• Applications: Displays, Monitors, TV
• Interface: Analog
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 80-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

0E
0E
0E
0E
0E
REV. B
5 Hsync Output Polarity
This bit determines the polarity of the Hsync output and
the SOG output. Table XI shows the effect of this option.
SYNC indicates the logic state of the sync pulse.
Setting
0
1
The default setting for this register is 0.
4 Active Hsync Override
This bit is used to override the automatic Hsync selection,
To override, set this bit to Logic 1. When overriding, the
active Hsync is set via Bit 3 in this register.
Override
0
1
The default for this register is 0.
3 Active Hsync Select
This bit is used under two conditions. It is used to select
the active Hsync when the override bit is set (Bit 4). Alter-
nately, it is used to determine the active Hsync when not
overriding but both Hsyncs are detected.
Select
0
1
The default for this register is 0.
2 Vsync Output Invert
This bit inverts the polarity of the Vsync output. Table
XIV shows the effect of this option.
Setting
0
1
The default setting for this register is 0.
1 Active Vsync Override
This bit is used to override the automatic Vsync selection.
To override, set this bit to Logic 1. When overriding, the
active interface is set via Bit 0 in this register.
Override
0
1
The default for this register is 0.
Table XIII. Active HSYNC Select Settings
Table XV. Active Vsync Override Settings
Table XI. Hsync Output Polarity Settings
Table XIV. Vsync Output Invert Settings
Table XII. Active Hsync Override Settings
Result
Autodetermines the Active Interface
Override, Bit 3 Determines the Active Interface
Result
Autodetermine the Active Vsync
Override, Bit 0 Determines the Active Vsync
SYNC
Logic 1 (Positive Polarity)
Logic 0 (Negative Polarity)
Vsync Output
Invert
No Invert
Result
HSYNC Input
Sync-on-Green Input
–19–
0E
0F
0F
0F
0 Active Vsync Select
This bit is used to select the active Vsync when the over-
ride bit is set (Bit 1).
Select
0
1
The default for this register is 0.
7 Clamp Input Signal Source
This bit determines the source of clamp timing.
Clamp Function
0
1
A 0 enables the clamp timing circuitry controlled by clamp
placement and clamp duration. The clamp position and
duration is counted from the leading edge of Hsync.
A 1 enables the external CLAMP input pin. The three
channels are clamped when the CLAMP signal is active.
The polarity of CLAMP is determined by the Clamp
Polarity bit (Register 0FH, Bit 6).
The power-up default value is Clamp Function = 0.
6 Clamp Input Signal Polarity
This bit determines the polarity of the externally provided
CLAMP signal.
Clamp Function
1
0
A Logic 1 means that the circuit will clamp when CLAMP is
low, and it will pass the signal to the ADC when CLAMP is
high.
A Logic 0 means that the circuit will clamp when CLAMP
is high, and it will pass the signal to the ADC when
CLAMP is low.
The power-up default value is Clamp Polarity = 1.
5 Coast Select
This bit is used to select the active Coast source. The
choices are the Coast Input Pin or Vsync. If Vsync is se-
lected the additional decision of using the Vsync input
pin or the output from the sync separator needs to be
made (Register 0E, Bits 1, 0).
Table XIX. Power-Down Settings
Select
0
1
Table XVIII. Clamp Input Signal Polarity Settings
Table XVII. Clamp Input Signal Source Settings
Table XVI. Active Vsync Select Settings
Result
Coast Input Pin
Vsync (See above Text)
Result
Vsync Input
Sync Separator Output
Function
Internally Generated Clamp Signal
Externally Provided Clamp Signal
Function
Active Low
Active High
AD9883A