LFXP3E-3QN208I Lattice, LFXP3E-3QN208I Datasheet - Page 153

• Manufacturer Part Number: LFXP3E-3QN208I
• Description: IC FPGA 3.1KLUTS 136I/O 208-PQFP
• Manufacturer: Lattice

Specifications of LFXP3E-3QN208I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
or
LOCATE PGROUP “ vref_pg1” BANK 2;
LOCATE PGROUP “ vref_pg2” BANK 2;
The second example show V
V
which bank V
bank.
If the PGROUP VREF is not used, the software will automatically group all pins that need the same V
voltage. This preference is most useful when there is more than one bus using the same reference voltage and the
user wants to associate each of these buses to different V
Differential I/O Implementation
The LatticeECP/EC and LatticeXP devices support a variety of differential standards as detailed in the following
section.
LVDS
True LVDS (LVDS25) drivers are available on the left and right side of the devices. LVDS input support is provided
on all sides of the device. All four sides support LVDS using complementary LVCMOS drivers with external resis-
tors (LVDS25E).
Please refer to the LatticeECP/EC and LatticeXP data sheets for a more detailed explanation of these LVDS imple-
mentations.
BLVDS
All single-ended sysIO buffer pairs in the LatticeECP family support the Bus-LVDS standard using complementary
LVCMOS drivers with external resistors.
Please refer to the LatticeECP/EC and LatticeXP data sheets to learn more about BLVDS implementation.
RSDS
All single-ended sysIO buffers pairs in the LatticeECP family support the RSDS standard using complementary
LVCMOS drivers with external resistors. This mode uses LVDS25E with an alternative resistor pack.
Please refer to the LatticeECP/EC and LatticeXP data sheets for a detailed explanation of RSDS implementation.
LVPECL
All the sysIO buffers will support LVPECL inputs. LVPECL outputs are supported using a complementary LVCMOS
driver with external resistors.
Please refer to the LatticeECP/EC and LatticeXP data sheets for further information on LVPECL implementation.
Differential SSTL and HSTL
All single-ended sysIO buffers pairs in the LatticeECP family support differential SSTL and HSTL. Please refer to
the LatticeECP/EC and LatticeXP data sheets for a detailed explanation of Differential HSTL and SSTL implemen-
tation.
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
e-mail:
REF
must then be locked to either V
[phone] (Outside North America)
[e-mail]
REF
group should be located. The software will then assign these to either V
REF
groups, “vref_pg1” assigned to V
REF1
or V
REF2
using LOCATE preference. Or, the user can simply designate to
8-13
REF
resources.
REF
“ref1” and “vref_pg2” assigned to “ref2”.
LatticeECP/EC and LatticeXP
sysIO Usage Guide
REF1
or V
REF
REF2
reference
of the