LFXP3E-3QN208I Lattice, LFXP3E-3QN208I Datasheet - Page 229

• Manufacturer Part Number: LFXP3E-3QN208I
• Description: IC FPGA 3.1KLUTS 136I/O 208-PQFP
• Manufacturer: Lattice

Specifications of LFXP3E-3QN208I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 10-11. Software Primitive Implementation for Memory READ
Read Timing Waveforms
Figure 10-12 and Figure 10-13 show READ data transfer for two cases based on the results of the DQS Transition
detector logic. This circuitry decides whether or not to invert the phase of FPGA system CLK to the synchronization
registers based on the relative phases of PRMBDET and CLK.
The signals A, B and C illustrate the Read Cycle half clock transfer at different stages of IDDRX registers. The first
stage of the register captures data on the positive edge as shown by signal A and negative edge as shown by sig-
nal B. The data stream A goes through an additional half clock cycle transfers shown by signal C. Phase aligned
data streams B and C are presented to the next stage registers clocked by the FPGA CLK
• Case 1 – If CLK = 0 on the 1st PRMBDET transition, then DDRCLKPOL = 0, hence no inversion required.
• Case 2 – If CLK=1 on the 1st PRMBDET then DDRCLKPOL = 1, the system clock (CLK) needs to be
(Figure 10-12)
inverted before it is used for synchronization. (Figure 10-13)
dqs
dq
uddcntl
read
reset
clk
ce
RST
UDDCNTL
DQSI
CLK
READ
DQSBUFB
DQSDLL
DQSDEL
DQSDEL
6
DDRCLKPOL
PRMBDET
10-10
DQSO
DQSC
LOCK
D
ECLK
DDRCLKPOL
LSR
CE
SCLK
LatticeECP/EC and LatticeXP
IDDRXB
QA
QB
DDR Usage Guide
datain_p
datain_n
dqsc
prmbdet
lock