LFXP3E-3QN208I Lattice, LFXP3E-3QN208I Datasheet - Page 259

• Manufacturer Part Number: LFXP3E-3QN208I
• Description: IC FPGA 3.1KLUTS 136I/O 208-PQFP
• Manufacturer: Lattice

Specifications of LFXP3E-3QN208I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

LatticeECP/EC and LatticeXP
Lattice Semiconductor
sysCLOCK PLL Design and Usage Guide
CLKOS Output with Phase and Duty Cycle Select
The sysCLOCK PLL auxiliary clock output, CLKOS, is a signal available for selection as a primary clock. The
CLKOS is used when phase shift and/or duty cycle adjustment is desired. The programmable phase shift allows for
different phase in increments of 45° to 315°. The duty select feature provides duty select in 1/8th of the clock
period.
CLKOK Output with Lower Frequency
The CLKOK is used when a lower frequency is desired. It is a signal available for selection as a primary clock.
Dynamic Delay Control I/O Ports
Refer to Table 11-1 and Table 11-3 for detailed information.
LOCK Output
The LOCK output provides information about the status of the PLL. After the device is powered up and the input
clock is valid, the PLL will achieve lock within the specified lock time. Once lock is achieved, the PLL lock signal will
be asserted. If, during operation, the input clock or feedback signals to the PLL become invalid, the PLL will lose
lock. The LOCK signal is available to the FPGA routing to implement generation of RST.
Note: For LatticeECP/EC, RST must be asserted to restart the locking process after losing lock. Refer to the
LatticeECP/EC Family Data Sheet for the RST pulse width requirement. For LatticeXP, RST may be tied to GND.
PLL Attributes
The PLL utilizes several attributes that allow the configuration of the PLL through source constraints. The following
section details these attributes and their usage.
FIN
The input frequency can be any value within the specified frequency range based on the divider settings.
CLKI_DIV, CLKFB_DIV, CLKOP_DIV, CLKOK_DIV
These dividers determine the output frequencies of each output clock. The user is not allowed to input an invalid
combination; determined by the input frequency, the dividers, and the PLL specifications.
Frequency_Pin_CLKI, Frequency_Pin_CLKOP and Frequency_Pin_CLKOK
These output clock frequencies determine the divider values.
FDEL
The FDEL attribute is used to pass the Delay Adjustment step associated with the Output Clock of the PLL. This
allows the user to advance or retard the Output Clock by the step value passed multiplied by 250ps(nominal). The
step ranges from -8 to +8 resulting the total delay range to +/- 2ns.
PHASEADJ
The PHASEADJ attribute is used to select Coarse Phase Shift for CLKOS output. The phase adjustment is pro-
grammable in 45° increments.
DUTY
The DUTY attribute is used to select the Duty Cycle for CLKOS output. The Duty Cycle is programmable at 1/8 of
the period increment.
FB_MODE
There are three sources of feedback signals that can drive the CLKFB Divider: internal, clocktree and external
feedback. Clocktree feedback is used by default. Internal feedback takes the CLKOP output at CLKOP Divider out-
put before the Clocktree to minimize the feedback path delay. The external feedback is driven from the pin.
DELAY_CNTL
11-3