LFXP3E-3QN208I Lattice, LFXP3E-3QN208I Datasheet - Page 276

• Manufacturer Part Number: LFXP3E-3QN208I
• Description: IC FPGA 3.1KLUTS 136I/O 208-PQFP
• Manufacturer: Lattice

Specifications of LFXP3E-3QN208I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Appendix A. Clock Preferences
A few key clock preferences are introduced below. Refer to the ‘Help’ file for other preferences and detailed infor-
mation.
ASIC
The following preference command assigns a phase of 90° to the CIMDLLA CLKOP.
FREQUENCY
The following physical preference command assigns a frequency of 100 MHz to a net named clk1.
The following preference specifies a hold margin value for each clock domain.
MAXSKEW
The following command assigns a maximum skew of 5 ns to a net named NetB.
MULTICYCLE
The following command will relax the period to 50 ns for the path starting at COMPA to COMPB (NET1).
PERIOD
The following command assigns a clock period of 30 ns to the port named Clk1.
PROHIBIT
This command prohibits the use of a primary clock to route a clock net named bf_clk.
CLOCK_TO_OUT
Specifies a maximum allowable output delay relative to a clock.
Below are two preferences using both the CLKPORT and CLKNET keywords showing the corresponding scope of
TRACE reporting.
The CLKNET will stop tracing the path before the PLL, so you will not get PLL compensation timing numbers.
The above preference will yield the following clock path:
ASIC "my_pll" TYPE "EXHXPLLB" CLKOS_PHASE=90;
FREQUENCY NET "clk1" 100 MHz;
FREQUENCY NET "RX_CLKA_CMOS_c" 100.000 MHz HOLD_MARGIN 1 ns;
MAXSKEW NET "NetB" 5 NS;
MULTICYCLE "PATH1" START COMP "COMPA" END COMP "COMPB" NET "NET1" 50 NS ;
PERIOD PORT "Clk1" 30 NS;
PROHIBIT PRIMARY NET "bf_clk";
CLOCK_TO_OUT PORT "RxAddr_0" 6.000000 ns CLKNET "pll_rxclk" ;
11-20
sysCLOCK PLL Design and Usage Guide
LatticeECP/EC and LatticeXP