LFXP3E-3QN208I Lattice, LFXP3E-3QN208I Datasheet - Page 321

• Manufacturer Part Number: LFXP3E-3QN208I
• Description: IC FPGA 3.1KLUTS 136I/O 208-PQFP
• Manufacturer: Lattice

Specifications of LFXP3E-3QN208I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 14-2. ispTRACY Core Generator Features and Descriptions
Lattice Semiconductor
Number of Core
ispTRACY Core
Size Comparison Logic
Event Counter Size
Trigger Same as Trace
Trigger Bus Size
Trace Bus Size
Trace Memory Depth
Sample_After_Trigger Mode Logic
Number of Edge Trigger Signals
Number of Level Trigger Signals
Trigger Input Logic
Trigger Output Logic
Generate
Cancel
Help
Feature
The number of ispLA(s) in an XPGA can be either 1, 2, 3, ..., or 16. The ispLA needs to be
configured before use. After [Generate] button is clicked, the ispTRACY software will gen-
erate the required logic for each ispLA based on its own configuration.
Lists the ispLA.
The comparison logic can compare the trigger bus with the patterns setting by the user.
This field needs to be ON for ">", ">=", "<", "<=" comparison. If it's OFF, only = (equal) and
<> (not equal) comparison can be preformed.
This field configures the size of the event counter. If this field is 8, the counter can be set to
the value from 1 to 255. If this field is 16, the counter can be set to the value from 1 to
65535. If this field is "None", the counter logic is removed (i.e. counter value N always
equal 1). If the counter value is set to N, then when the pattern occurs N times, the corre-
sponding event will be TRUE.
If this is ON, the trace bus and trigger bus are the same bus. If this is OFF, the trace bus
and trigger bus are different and they can have different bus sizes.
This specifies the trigger bus size. It can be 4, 5, 6, ..., up to 128.
This specifies the trace bus size. It can be a multiple of 8 up to 256 (i.e. 8, 16, 24, 32,
40,..., up to 256).
This is the depth of the trace memory. It defines the number of trace bus samples that
ispLA can capture. This field can be set be set to 512, 1024, 2048, or 4096. It can also be
set to 256 if the trace bus size is a multiple of 16 (i.e. 16, 32, 48, etc.).
The field causes the Sample_After_Trigger mode logic to be removed or not. If this is ON,
the trace mode can be set to "One Shot" mode or "Sample After Trigger" mode.
If this is OFF, the trace can only be running at "One Shot" mode. When this logic is turned
off, the ispLA will use less logic.
The trigger bus signals can be either edge sensitive signals or level sensitive signals. The
level sensitive trigger signals can only be set to 0, 1 or X (don't care). The edge sensitive
trigger signals can be set to 0, 1, X, R (rising edge), F (falling edge) or B (both edges).
This field specifies the number of edge sensitive trigger signals.
This field specifies the number of level sensitive trigger signals. Note that (Number of
Edge Trigger Signals) + (Number of Level Trigger Signals) = (Trigger Bus Size).
This specifies if the "Trigger Input" logic exists. If this field is "None", the logic will be
removed and the trigger condition can only be set using EV0 and EV1.
If this field is set to "Pin" the trigger input logic exists and the trigger input should come
from an ispXPGA device I/O pin. The trigger input can be set to either active low or active
high.
This specifies if the "Trigger Output" logic exists. If this field is "None", the logic will be
removed. If this field is set to "Pin" the trigger output logic exists and the trigger output
should go out through an XPGA device I/O pin. If this is set to "ispLA", the trigger output
will be connected to the trigger input of other ispLAs.
You must choose "Trigger Input Logic" of the other ispLAs to be this ispLA. Same as the
trigger input, the trigger output can be set to either active low or active high.
At least one ispLA should have this option set to "Pin."
Generates the core.
Cancels the action and closes the dialog box without saving any changes.
Displays online Help topics for this dialog box.
14-3
Description
Lattice ispTRACY Usage Guide