LFXP3E-3QN208I Lattice, LFXP3E-3QN208I Datasheet - Page 38

• Manufacturer Part Number: LFXP3E-3QN208I
• Description: IC FPGA 3.1KLUTS 136I/O 208-PQFP
• Manufacturer: Lattice

Specifications of LFXP3E-3QN208I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 2-9. Characteristics of Normal, Off and Sleep Modes
SLEEPN Pin Characteristics
The SLEEPN pin behaves as an LVCMOS input with the voltage standard appropriate to the VCC supply for the
device. This pin also has a weak pull-up typically in the order of 10µA along with a Schmidt trigger and glitch filter
to prevent false triggering. An external pull-up to V
device stays in normal operation mode. Typically the device enters Sleep Mode several hundred ns after SLEEPN
is held at a valid low and restarts normal operation as specified in the Sleep Mode Timing table. The AC and DC
specifications portion of this data sheet show a detailed timing diagram.
Configuration and Testing
The following section describes the configuration and testing features of the LatticeXP family of devices.
IEEE 1149.1-Compliant Boundary Scan Testability
All LatticeXP devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test access
port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan
path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in
and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port
consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage V
operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards.
For more details on boundary scan test, please see information regarding additional technical documentation at
the end of this data sheet.
Device Configuration
All LatticeXP devices contain two possible ports that can be used for device configuration and programming. The
test access port (TAP), which supports serial configuration, and the sysCONFIG port that supports both byte-wide
and serial configuration.
The non-volatile memory in the LatticeXP can be configured in three different modes:
The SRAM configuration memory can be configured in three different ways:
SLEEPN Pin
Static Icc
I/O Leakage
Power Supplies VCC/VCCIO/VCCAUX
Logic Operation
I/O Operation
JTAG and Programming circuitry
EBR Contents and Registers
• In sysCONFIG mode via the sysCONFIG port. Note this can also be done in background mode.
• In 1532 mode via the 1149.1 port.
• In background mode via the 1149.1 port. This allows the device to be operated while reprogramming takes
• At power-up via the on-chip non-volatile memory.
• In 1532 mode via the 1149.1 port SRAM direct configuration.
• In sysCONFIG mode via the sysCONFIG port SRAM direct configuration.
place.
Characteristic
Typical <100mA
Normal Range
User Defined
User Defined
Operational
Maintained
Normal
<10µA
High
CC
is recommended when Sleep Mode is not used to ensure the
2-26
Non Operational
Non-operational
Non-maintained
Tri-state
<1mA
Off
Off
—
0
LatticeXP Family Data Sheet
Non-operational
Non operational
Non-maintained
Typical <100uA
Normal Range
Tri-state
<10µA
Architecture
Sleep
Low
CCJ
and can