LFXP3E-3QN208I Lattice, LFXP3E-3QN208I Datasheet - Page 266

• Manufacturer Part Number: LFXP3E-3QN208I
• Description: IC FPGA 3.1KLUTS 136I/O 208-PQFP
• Manufacturer: Lattice

Specifications of LFXP3E-3QN208I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Equations for Generating Input and Output Frequency Ranges
The values of f
MIN
ranges become the limits for the specific divider settings used in the design.
Table 11-4. Frequency Limits
The divider names are abbreviated with legacy names as:
for use in the equations below.
f
From the loop:
From the loop:
Substitute (1) in (2) yields:
Arrange (3):
From equation (4):
f
From the loop:
Equation (5) becomes:
VCO
PFD
and f
• CLKI DIVIDER:M
• CLKFB DIVIDER:N
• CLKOP DIVIDER:V
• CLKOK DIVIDER:K
Constraint
Constraint
f
f
f
f
f
f
f
f
f
OUT
VCO
VCO
IN
INMIN
INMAX
PFD
IN
INMIN
OUTMAX
= (f
= f
= f
= f
= f
= f
PFD
VCO
= ((f
= f
IN,
= (f
IN
IN
OUT
IN
PFDMIN
are the calculated frequency ranges based on the divider settings. These calculated frequency
f
/ M
* M
* (N/M)
* (N/M) * V
VCOMAX
OUT
VCOMIN
/ (V*N))*M
* V
f
f
f
f
CLKI Divider
CLKFB Divider
CLKOP Divider
CLKOK Divider
Maximum (N*V)
f
Note: Refer to data sheet for the latest data.
IN
OUT
OUTK
VCO
PFD
and f
* M = 25 * M (assume f
(f
(Hz)
/(V*N))*M
/(V*N))*M
IN
Parameter
VCO
/M) (Hz)
are the absolute frequency ranges for the PLL. The values of f
PFDMIN
LatticeECP/EC
1 to 16
1 to 16
11-10
= 25)
32
2, 4, 6, 8,.. ,126, 128
sysCLOCK PLL Design and Usage Guide
See Table 11-2
Note 1
Note 1
Note 1
Note 1
Note 1
LatticeECP/EC and LatticeXP
LatticeXP
1 to 15
1 to 15
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
30
INMIN,
f
INMAX,
f
OUT-