LFXP3E-3QN208I Lattice, LFXP3E-3QN208I Datasheet - Page 226

• Manufacturer Part Number: LFXP3E-3QN208I
• Description: IC FPGA 3.1KLUTS 136I/O 208-PQFP
• Manufacturer: Lattice

Specifications of LFXP3E-3QN208I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 10-5. DQSBUFB Ports
Notes:
READ Pulse Generation
The READ signal to the DQSBUFB block is internally generated in the FPGA core. The Read signal will go high
when the READ command to control the DDR SDRAM is initially asserted. This should normally precede the DQS
preamble by one cycle yet may overlap the trailing bits of a prior read cycle. The DQS Detect circuitry of the Lat-
ticeECP/EC and LatticeXP devices require the falling edge of the READ signal to be placed within the preamble
stage.
The preamble state of the DQS can be detected using the CAS latency and the round trip delay for the signals
between the FPGA and the memory device. Note that the internal FPGA core generates the READ pulse. The rise
of the READ pulse needs to coincide with the initial READ Command of the Read Burst and needs to go low before
the Preamble goes high.
Figure 10-8 shows the READ Pulse Timing Example with respect to the PRMBDET signal.
Figure 10-8. READ Pulse Generation
1. The DDR Clock Polarity output from this block should be connected to the DDCLKPOL inputs of the input
OK
FAIL
FAIL
OK
register blocks (IDDRXB).
PRMBDET
DQSI
CLK
READ
DQSDEL
DQSO
DQSC
DDRCLKPOL
PRMBDET
Port Name
READ
READ
READ
READ
DQS
PRIOR READ CYCLE
I/O
O
O
O
O
I
I
I
I
POSTAMBLE
DQS strobe signal from memory
System CLK
Read generated from the FPGA core
DQS delay from the DQSDLL primitive
Delayed DQS Strobe signal, to the input capture register block
DQS Strobe signal before delay, going to the FPGA core logic
DDR Clock Polarity signal
Preamble detect signal, going to the FPGA core logic
PREAMBLE
VTH
10-7
TRANSITION
FIRST DQS
Definition
LatticeECP/EC and LatticeXP
DDR Usage Guide
POSTAMBLE