TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 178

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

8.3.14
8.3.15
Arbitration Among DMA Channels
DMA channels that use the internal bus (G-Bus). There are two methods for determining priority: the
round robin method and the fixed priority method. (See Figure 8.3.7.) The Round Robin Priority bit
(RRPT) of the DMA Master Control Register (DMMCR) selects the priority method.
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Restrictions in Access to PCI Bus
to the PCI Bus.
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supported. Data transfer is not performed, but no error is detected.
Channel 0
The DMA Controller has an on-chip DMA Channel Arbiter that arbitrates bus ownership among four
The PCI Controller detects a bus error if the DMA Controller performs one of the following accesses
In addition, Single Address transfers between an external I/O device and the PCI Bus are not
Fixed priority (DMMCR.RRPT = 0)
As shown below, Channel 0 has the highest priority and Channel 3 has the lowest priority.
Round Robin method (DMMCR.RRPT = 1)
The last channel to perform DMA transfer has the lowest priority.
Burst transfer exceeding 8 double words (PCICSTATUS.TLB)
Address Increment value –8 Burst transfer (PCICSTATUS.NIB)
Address Increment Value 0 Burst transfer (PCICSTATUS.ZIB)
Dual Address Burst transfer when the setting for DMSARn, DMDARn, or DMCNTRn is not a
double word boundary (PCICSTATUS.IAA)
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After CH0 DMA transfer execution: CH1 > CH2 > CH3 > CH0
After CH1 DMA transfer execution: CH2 > CH3 > CH0 > CH1
After CH2 DMA transfer execution: CH3 > CH0 > CH1 > CH2
After CH3 DMA transfer execution: CH0 > CH1 > CH2 > CH3
Channel 3
CH0 > CH1 > CH2 > CH3
Figure 8.3.7 DMA Channel Arbitration
Channel 1
b) Round Robin Priority is selected
a) Fixed Priority is selected
Channel 0
Channel 2
8-22
Channel 2
Chapter 8 DMA Controller
Channel 1
Channel 3