TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 65

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

ADDR[19]
ADDR[18]
ADDR[17:15]
ADDR[14:13]
ADDR[12]
ADDR[11:10]
ADDR[9]
ADDR[8:6]
ADDR[5]
Signal
PCI Controller Mode Select
Specifies the operating mode of the TX4937 PCI controller.
L = Satellite
H = Host
Select Shared I/O Pins
Specifies the function of the PIO[15:8]/CB[7:0] shared pins.
L = PIO[15:8]
H = CB[7:0]
Reserved
Used for testing. This signal will not be set to 0 upon booting.
Select SYSCLK Frequency
Specifies the division ratio of the SYSCLK frequency to the G-Bus
clock (GBUSCLK) frequency.
LL = 4 (SYSCLK frequency = GBUSCLK frequency/4)
LH = 3 (SYSCLK frequency = GBUSCLK frequency/3)
HL = 2 (SYSCLK frequency = GBUSCLK frequency/2)
HH = 1 (SYSCLK frequency = GBUSCLK frequency)
TX4937 Endian Mode
Specifies the TX4937 endian mode.
L = Little endian
H = Big endian
Select PCI Clock Frequency
Specifies the division ratio of the PCI bus clock (PCICLK[5:0]) to the
TX49/H3 core clock (CPUCLK). Initial value of CCFG[12] is 0.
LL = 8 (PCICLK frequency = CPUCLK frequency/8)
LH = 9 (PCICLK frequency = CPUCLK frequency/9)
HL = 10 (PCICLK frequency = CPUCLK frequency/10)
HH = 11 (PCICLK frequency = CPUCLK frequency/11)
PIO[4:2]/ACLC/DMAREQ[2]/DMAACK[2] Select
Specifies whether PIO[4:2]/DMAREQ[2]/DMAACK[2] signals are
used as PIO or AC-link interface signals.
L = PIO
H = AC-link interface
Select Boot Memory and Device Clock Frequency
Specifies the clock division ratio for external bus controller channel 0
upon booting (refer to Section “7.3.8 Clock Options”).
HHH = Device connected to channel 0 of the external bus controller
HHL = Device connected to channel 0 of the external bus controller
HLH = Device connected to channel 0 of the external bus controller
HLL = Device connected to channel 0 of the external bus controller
LHH =PCI boot
LHL = Reserved
LLH and LLL = Reserved
Select SDRAM device
Select initial setting derivability of SDRAM interface signals
L = 8mA
H = 16mA
ADDR[19:0], CKE, RAS*, CAS*, WE*, SDCS[3:0], SDCLK[3:0],
SDCLKIN
Table 3.2.2 Boot Configuration Specified with the ADDR[19:0] Signals (1/2)
(Clock division rate = 1/1)
(Clock division rate = 1/2)
(Clock division rate = 1/3)
(Clock division rate = 1/4)
Description
3-11
ADDR[8]:
EBCCR0.ME
ADDR[7:6]
EBCCR0.SP
CCFG. PCIMODE
PCFG. SEL1
CCFG. SYSSP
CCFG. ENDIAN
CCFG. PCIDIVMODE CGRESET* deassert
PCFG.SEL2
PCFG[53:40]
Corresponding
Register Bit
Chapter 3 Signals
⎯
RESET* deassert edge
RESET* deassert edge
CGRESET* deassert
edge
RESET* deassert edge
edge
RESET* deassert edge
RESET* deassert edge
RESET* deassert edge
Determined at
Configuration
⎯