TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 48

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

1.2.1
1.2.2
Features of the TX49/H3 core
Toshiba developed.
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Features of TX4937 peripheral functions
(1) External Bus Controller (EBUSC)
The TX49/H3 core is a high-performance, low power consumption 64-bit RISC CPU core that
64-bit operation
32 64-bit integer general-purpose registers
64 GB physical address space
Optimized 5-stage pipeline
Instruction Set
Upwards compatible MIPS III ISA
Added 3-operand multiply instruction, MAC (multiply accumulate) instruction, and PREF (pre-
fetch) instruction
Supports 32 KB Instruction cache, 32 KB Data cache, 4-way set associative, and the lock function
MMU (Memory Management Unit)
48 double entry (odd/even) joint TLB
On-chip IEEE754-compatible single-precision and double-precision FPU
4-stage write buffer mounted
Debugging Support Unit: EJTAG
external I/O devices.
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The External Bus Controller generates the signals necessary to control external memory and
Has 8-channel Chip Select signal, can control up to 8 external devices
Supports access of ROM (mask ROM, page mode ROM, EPROM, EEPROM), SRAM, Flash
ROM, and I/O devices
Can set data bus width to 32 bits, 16 bits, or 8 bits for each channel
System clock for External Bus Controller (SYSCLK) frequency is up to 133 MHz (For
relationship between CPU clock and this system clock, see Section 6.1)
Can select full speed, 1/2 speed, 1/3 speed , or 1/4 speed for each channel
Can set timing for each channel
Can set up and set the Hold interval of the Address, Chip Enable, Write Enable, and Output
Enable signals
Supports access of devices with a 32-bit wide data bus in memory sizes from 1 MB to 1 GB.
Supports access of devices with a 16-bit wide data bus in memory sizes from 1 MB to 512
MB. Supports access of devices with an 8-bit wide data bus in memory sizes from 1 MB to
256 MB.
1-2
Chapter 1 Overview and Features