TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 227

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

9.3.5
9.3.5.1
9.3.5.2
Low Power Consumption Function
Power Down Mode, Self-Refresh Mode
Refresh mode. Memory data is lost in the case of the Power Down mode since Memory Refresh is
not performed, but the amount of power consumed is reduced the most. Memory data is not lost in
the case of the Self-Refresh mode.
to issue the Power Down Mode command. Similarly, SDRAM is set to the Self-Refresh mode by
issuing the Self-Refresh Mode command. The SDRAMC terminates internal refresh circuit
operation after one of these commands has been issued. Issuing the Normal Mode command
returns operation to normal.
SDRAM is automatically set to the Power Down mode when memory access is not being
performed. The SDRAMC internal refresh circuit will continue operating, so there will be no loss
of memory data.
SDRAM is set to the Power Down mode or the Self-Refresh mode, then the Power Down mode
and Self-Refresh mode will automatically terminate, and memory access will be performed.
Mode command or the Self-Refresh Mode command, the next memory access starts after 10
SDCLK cycles pass. This latency sufficiently follows the stipulated time from Power Down to
first access of the SDRAM.
when set in the Power Down mode, then add 1 SDCLK cycle more of access latency than when
not in the Power Down mode.
Advanced CKE
clock cycle. This function is set using the Address CKE bit (SDCTR.ACE) of the SDRAM Timing
Register.
when the power to the TX4937 itself is cut. Since CKE On/Off becomes 1 cycle faster, it is
possible to delay CKE by 1 clock cycle using external power consumption control logic. Please set
the SDRAM to the Self-Refresh mode before using this function.
memory access is requested while in the Power Down mode, two more SDCLK cycles of latency
are added than would be the case when not in the Power Down mode.
SDRAM has two low power consumption modes called the Power Down mode and the Self-
SDRAM is set to the Power Down mode by using the SDRAM Command Register (SDCCMD)
When the Power Down Auto Entry bit (SDCTR.PDAE) of the SDRAM Timing Register is set,
If either the Memory Access, Memory Refresh, or Memory command is executed while
After returning from a low power consumption mode that was set by either the Power Down
If setting the Power Down Auto Entry bit automatically causes memory access to be requested
Advanced CKE is a function that speeds up the CKE assertion and deassertion timing by 1
Advanced CKE assumes that it will be used in a system where SDRAM data is saved even
When combining advanced CKE functionality with Power Down Auto Entry functionality and
9-11
Chapter 9 SDRAM Controller