TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 369

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

11.3.9
11.3.10 Software Reset
set when one of the following errors is detected: an overrun error, a parity error, or a framing error. An
interrupt is signaled if the Reception Error Interrupt Enable bit of the DMA/Interrupt Control Register
(SIDICRn) is set.
Interrupt Status Register (SISCISR) is set when a break is detected. The Break Detected bit (UBRKD)
remains set until it is cleared by the software. The Receiving Break bit (RBRKD) is automatically
cleared when a frame is received that is not a break.
bit (UPER), Framing Error bit (UFER), and the Receive Break bit (RBRKD). Each of these statuses is
updated when reception data is read from the Receive FIFO Register (SIRFIFOn).
Receive FIFO if either an error (Framing Error, Parity Error, or Overrun Error) or a Reception time out
(TOUT) is detected. If a Reception Error occurs during DMA transfer, use the Receive FIFO Reset bit
(RFRST) of the FIFO Control Register (SIFCRn) to clear the Receive FIFO. However, a software reset
will be required if a reception overrun error has occurred. Refer to “11.3.10 Software Reset” for more
information.
Reception Time Out
Status Register (SIDISR) is set under the following conditions.
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•
1.
2.
(SIFCR). This bit automatically returns to “0” after initialization is complete. This bit must be set again
since all SIO registers are initialized by software resets.
The Reception Error Interrupt bit (SIDISR.ERI) of the DMA/Interrupt Status Register (SIDISRn) is
The Break Detected bit (UBRKD) and the Receiving Break bit (RBRKD) of the Status Change
The status of the next reception data to be read is set to the Overrun Error bit (UOER), Parity Error
During DMA transfer, an error is signaled and DMA transfer stops with error data remaining in the
A Reception time out is detected and the Reception Time Out bit (TOUT) of the DMA/Interrupt
It is necessary to reset the FIFO and perform a software reset in the following situations.
Software reset is performed by setting the Software Reset bit (SWRST) of the FIFO Control Register
DMA transfer mode (SIDICRn.RDE = 1):
Non-DMA transfer mode (SIDICRn.RDE = 0):
the 2 frames (2 Bytes) after the last reception has elapsed
regardless of whether reception data exists in the Receive FIFO
After transmission data is set in FIFO, etc., transmission started but stopped before its completion
An overrun occurred during data reception
When at least 1 Byte of reception data exists in the Receive FIFO and the data reception time for
When the data reception time for the 2 frames (2 Bytes) after the last reception has elapsed
11-9
Chapter 11 Serial I/O Port