TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 184

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

18:17
Bit
26
25
24
23
22
21
20
19
Mnemonic
REVBYTE
ACKPOL
EGREQ
CHRST
REQPL
DNCTL
DBINH
SBINH
CHDN
Destination Burst
Inhibit
Source Burst
Inhibit
Channel Reset
Reverse Byte
Acknowledge
Polarity
Request Polarity
Edge Request
Chain Complete
DONE Control
Field Name
Figure 8.4.2 DMA Channel Control Register (2/4)
Destination Burst Inhibit (Default: 0)
During Dual Address transfer, this bit sets whether to perform Burst
transfer or Single transfer on a Write cycle to the address set from FIFO to
DMDARn when Burst transfer is set by DMCCRn.XFSZ. Refer to “8.3.8.2
Burst Transfer During Dual Address Transfer” for more information.
The settings of this bit have no effect during Single Address transfers.
1: Multiple Single transfers are executed.
0: Burst transfer is executed.
Source Burst Inhibit (Default: 0)
During Dual Address transfer, this bit sets whether to perform Burst
transfer or Single transfer on a Read cycle to the FIFO from the address
set to DMSARn when Burst transfer is set by DMCCRn.XFSZ. Refer to
“8.3.8.2 Burst Transfer During Dual Address Transfer” for more
information.
The settings of this bit have no effect during Single Address transfers.
1: Multiple Single transfers are executed.
0: Burst transfer is executed.
Channel Reset (Default: 1)
This bit is used fo initializing channels. The DMCCRn.XFACT,
DMCCRn.CHNEN, and DMCSRn bits are all cleared. In addition, all
channel logic and interrupts from channels are cleared and bus ownership
requests to the DMA Channel Arbiter are also reset. The software must
clear this bit before operating a channel.
1: Reset channel
0: Enable channel
Reverse Bytes (Default: 0)
This bit specifies whether to reverse the byte order during a Dual Address
transfer when the Transfer Setting Size field (DMCCRn.XFSZ) setting is 8
bytes or more. Refer to “8.3.8.3 Double Word Byte Swapping” for more
information.
1: Reverses the byte order.
0: Does not reverse the byte order.
Acknowledge Polarity (Default: 0)
Specifies the polarity of the DMAACK[n] signal.
1: Asserts when the DMAACK[n] signal is High
0: Asserts when the DMAACK[n] signal is Low
Request Polarity (Default: 0)
Specifies the polarity of the DMAREQ[n] signal.
1: Asserts when the DMAREQ[n] signal is High.
0: Asserts when the DMAREQ[n] signal is Low.
Edge Request (Default: 0)
Specifies the method for detecting DMA requests by the DMAREQ[n]
signal.
1: DMAREQ[n] signal is Edge Detect.
0: DMAREQ[n] signal is Level Detect.
Chain Done (Default: 0)
Selects control by the DMADONE* signal. See “8.3.3.4 DMA Controller”
for more information.
1: Assertion of the DMADONE* signal controls the overall Chain DMA
0: Assertion of the DMADONE* signal controls DMA transfer according to
Done Control (Default: 00)
Specifies the input/output mode of the DMADONE* signal. Refer to
“8.3.3.4 DMADONE* Signal” for more information.
00: DMADONE* signal becomes the input signal, but input is ignored.
01: DMADONE* signal becomes the input signal.
10: DMADONE* signal becomes the output signal.
11: DMADONE* signal becomes the open drain input/output signal.
transfer.
the DMA Channel Register setting at that time.
8-28
Description
Chapter 8 DMA Controller
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W