FAN5234QSCX_NL Fairchild Semiconductor, FAN5234QSCX_NL Datasheet - Page 6

• Manufacturer Part Number: FAN5234QSCX_NL
• Manufacturer: Fairchild Semiconductor

Specifications of FAN5234QSCX_NL

• Dc To Dc Converter Type: Synchronous Buck Controller/PWM DC to DC Controller
• Number Of Outputs: 1
• Pin Count: 16
• Input Voltage: 5 to 24V
• Output Voltage: 0.9 to 5.5V
• Package Type: QSOP
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Operating Temperature (min): -10C
• Operating Temperature (max): 85C
• Lead Free Status / Rohs Status: Compliant

PRODUCT SPECIFICATION
The voltage at the positive input of the error amplifier is lim-
ited by the voltage at the SS pin which is charged with a
5mA current source. Once C
the output voltage will be in regulation. The time it takes SS
to reach 0.9V is:
where T
When SS reaches 1.5V, the Power Good outputs are enabled
and hysteretic mode is allowed. The converter is forced into
PWM mode during soft start.
Operation Mode Control
The mode-control circuit changes the converter’s mode of
operation from PWM to Hysteretic and visa versa, based
on the voltage polarity of the SW node when the lower
MOSFET is conducting and just before the upper MOSFET
turns on. For continuous inductor current, the SW node is
negative when the lower MOSFET is conducting and the
converters operate in fixed-frequency PWM mode as shown
in Figure 3. This mode of operation achieves high efficiency
at nominal load. When the load current decreases to the point
where the inductor current flows through the lower MOSFET
in the ‘reverse’ direction, the SW node becomes positive,
and the mode is changed to hysteretic, which achieves higher
efficiency at low currents by decreasing the effective switch-
ing frequency.
To prevent accidental mode change or "mode chatter" the
transition from PWM to Hysteretic mode occurs when the
SW node is positive for eight consecutive clock cycles
(see Figure 3). The polarity of the SW node is sampled at the
end of the lower MOSFET's conduction time. At the transi-
tion between PWM and hysteretic mode both the upper and
6
V
V
T
CORE
CORE
0.9
I
I
L
L
0.9
0
0
=
0.9 C
---------------------- -
is in seconds if C
×
5
SS
SS
SS
is in µ F.
has charged to VREF (0.9V)
Figure 3. Transitioning between PWM and Hysteretic Mode
1
PWM Mode
2
1
2
Hysteretic Mode
3
(1)
3
4
4
lower MOSFETs are turned off. The SW node will ‘ring’
based on the output inductor and the parasitic capacitance on
the SW node and settle out at the value of the output voltage.
The boundary value of inductor current, where current
becomes discontinuous, can be estimated by the following
expression.
Hysteretic Mode
Conversely, the transition from Hysteretic mode to PWM
mode occurs when the SW node is negative for 8 consecutive
cycles.
A sudden increase in the output current will also cause a
change from hysteretic to PWM mode. This load increase
causes an instantaneous decrease in the output voltage due to
the voltage drop on the output capacitor ESR. If the load
causes the output voltage (as presented at VSEN) to drop
below the hysteretic regulation level (20mV below VREF),
the mode is changed to PWM on the next clock cycle.
In hysteretic mode, the PWM comparator and the error
amplifier that provide control in PWM mode are inhibited
and the hysteretic comparator is activated. In hysteretic
mode the low side MOSFET is operated as a synchronous
rectifier, where the voltage across (V
and it is switched off when V
flowing back from the load) allowing the diode to block
reverse conduction.
5
I
LOAD DIS
6
(
5
7
)
=
8
(
--------------------------------------------------
V
6
2F
IN
Hysteretic Mode
SW
–
V
L
OUT
OUT
DS(ON)
)V
7
V
IN
OUT
goes positive (current
DS(ON)
8
REV. 1.0.10 5/3/04
) it is monitored,
PWM Mode
FAN5234
(2)