FAN5234QSCX_NL Fairchild Semiconductor, FAN5234QSCX_NL Datasheet - Page 8

• Manufacturer Part Number: FAN5234QSCX_NL
• Manufacturer: Fairchild Semiconductor

Specifications of FAN5234QSCX_NL

• Dc To Dc Converter Type: Synchronous Buck Controller/PWM DC to DC Controller
• Number Of Outputs: 1
• Pin Count: 16
• Input Voltage: 5 to 24V
• Output Voltage: 0.9 to 5.5V
• Package Type: QSOP
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Operating Temperature (min): -10C
• Operating Temperature (max): 85C
• Lead Free Status / Rohs Status: Compliant

PRODUCT SPECIFICATION
More accurate sensing can be achieved by using a resistor
(R1) instead of the R
This approach causes higher losses, but yields greater accu-
racy in both V
10mΩ) resistor.
Current limit (I
allow inductor current to rise in response to an output load
transient. Typically, a factor of 1.2 is sufficient. In addition,
since I
multiply I
use 25%). For example, in Figure 1 the target for I
would be:
Duty Cycle Clamp
During severe load increase, the error amplifier output can
go to its upper limit pushing a duty cycle to almost 100% for
significant amount of time. This could cause a large increase
of the inductor current and lead to a long recovery from a
transient, over-current condition, or even to a failure espe-
cially at high input voltages. To prevent this, the output of
the error amplifier is clamped to a fixed value after two clock
cycles if severe output voltage excursion is detected, limiting
the maximum duty cycle to
This circuit is designed to not interfere with normal PWM
operation. When FPWM is grounded, the duty cycle clamp
is disabled and the maximum duty cycle is 87%.
Gate Driver section
The Adaptive gate control logic translates the internal PWM
control signal into the MOSFET gate drive signals providing
necessary amplification, level shifting and shoot-through
protection. Also, it has functions that help optimize the IC
performance over a wide range of operating conditions.
Since MOSFET switching time can vary dramatically
from type to type and with the input voltage, the gate control
logic provides adaptive dead time by monitoring the
gate-to-source voltages of both upper and lower MOSFETs.
The lower MOSFET drive is not turned on until the
8
I
DC
LIMIT
Figure 5. Improving current sensing accuracy
LIMIT
MAX
LOAD(MAX)
> 1.2 × 1.25 × 1.6 × 6A ≈ 14A
is a peak current cut-off value, we will need to
=
DROOP
LIMIT
V
--------------
V
OUT
IN
DS(ON)
) should be set sufficiently high as to
and I
by the inductor ripple current (we’ll
+
ISNS
LDRV
PGND
---------
V
2.4
IN
LIMIT
of the FET as shown in Figure 5.
R
SENSE
. R1 is a low value (e.g.
Q2
LIMIT
(6)
gate-to-source voltage of the upper MOSFET has decreased
to less than approximately 1 volt. Similarly, the upper
MOSFET is not turned on until the gate-to-source voltage of
the lower MOSFET has decreased to less than approximately
1 Volt. This allows a wide variety of upper and lower MOS-
FETs to be used without a concern for simultaneous conduc-
tion, or shoot-through.
There must be a low-resistance, low-inductance path
between the driver pin and the MOSFET gate for the adap-
tive dead-time circuit to work properly. Any delay along that
path will subtract from the delay generated by the adaptive
dead-time circit and shoot-through may occur.
Frequency Loop Compensation
Due to the implemented current mode control, the modulator
has a single pole response with -1 slope at frequency deter-
mined by load
where R
type of modulator, Type 2 compensation circuit is usually
sufficient. To reduce the number of external components and
simplify the design task, the PWM controller has an inter-
nally compensated error amplifier. Figure 6 shows a Type 2
amplifier and its response along with the responses of a
current mode modulator and of the converter. The Type 2
amplifier, in addition to the pole at the origin, has a zero-pole
pair that causes a flat gain region at frequencies between the
zero and the pole.
F
F
18
14
V
0
P
Z
F
IN
PO
modulator
=
O
=
------------------- -
2πR
is load resistance, C
------------------- -
2πR
=
R1
REF
--------------------- -
2πR
1
1
2
2
F
C
C
P0
2
1
1
O
Figure 6. Compensation
=
C
=
O
R2
600kHz
6kHz
C2
C1
EA Out
F
O
Z
is load capacitance. For this
REV. 1.0.10 5/3/04
F
P
FAN5234
(8a)
(8b)
(7)