P89LPC931FDH NXP Semiconductors, P89LPC931FDH Datasheet - Page 37

• Manufacturer Part Number: P89LPC931FDH
• Description: MCU 8-Bit 89LP 80C51 CISC 8KB Flash 2.5V/3.3V 28-Pin TSSOP Tube
• Manufacturer: NXP Semiconductors

Specifications of P89LPC931FDH

• Package: 28TSSOP
• Device Core: 80C51
• Family Name: 89LP
• Maximum Speed: 18 MHz
• Ram Size: 256 Byte
• Program Memory Size: 8 KB
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 26
• Interface Type: I2C/SPI/UART
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 2

Philips Semiconductors
9397 750 14472
Product data
Fig 14. Watchdog timer in Watchdog mode (WDTE = ‘1’).
(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a
Watchdog
oscillator
feed sequence.
MOV WFEED1, #0A5H
MOV WFEED2, #05AH
PCLK
8.23.1 Software reset
8.23.2 Dual data pointers
8.22 Watchdog timer
8.23 Additional features
WDCON (A7H)
32
The watchdog timer causes a system reset when it underflows as a result of a failure
to feed the timer prior to the timer reaching its terminal count. It consists of a
programmable 12-bit prescaler, and an 8-bit down counter. The down counter is
decremented by a tap taken from the prescaler. The clock source for the prescaler is
either the PCLK or the nominal 400 kHz Watchdog oscillator. The watchdog timer can
only be reset by a power-on reset. When the Watchdog feature is disabled, it can be
used as an interval timer and may generate an interrupt.
watchdog timer in Watchdog mode. Feeding the watchdog requires a two-byte
sequence. If PCLK is selected as the Watchdog clock and the CPU is powered-down,
the watchdog is disabled. The watchdog timer has a time-out period that ranges from
a few s to a few seconds. Please refer to the P89LPC930/931 User’s Manual for
more details.
The SRST bit in AUXR1 gives software the opportunity to reset the processor
completely, as if an external reset or Watchdog reset had occurred. Care should be
taken when writing to AUXR1 to avoid accidental software resets.
The dual Data Pointers (DPTR) provides two different Data Pointers to specify the
address used with certain instructions. The DPS bit in the AUXR1 register selects
one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic ‘0’ so
that the DPS bit may be toggled (thereby switching Data Pointers) simply by
incrementing the AUXR1 register, without the possibility of inadvertently altering other
bits in the register.
PRE2
PRESCALER
PRE1
Rev. 05 — 15 December 2004
CONTROL REGISTER
PRE0
–
8-bit microcontrollers with two-clock 80C51 core
–
8-BIT DOWN
WDL (C1H)
COUNTER
WDRUN
WDTOF
P89LPC930/931
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Figure 14
WDCLK
002aaa423
RESET
see note (1)
shows the
SHADOW
REGISTER
FOR WDCON
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