PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 108

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

length equals the character length + optional parity bit. This is the user’s responsibility
by appropriate software settings.
Filling of the receive FIFO is controlled by a programmable threshold level.
Reception is stopped if
1. the receiver is deactivated by resetting the bit CCR3L: RAC bit, or
2. the CD signal goes inactive (if Carrier Detect Auto Start is enabled in register
3. the CMDRH: HUNT command is issued again, or
4. the Receiver Reset command ( CMDRH: RRES) is issued, or
5. a programmed Termination Character has been found (optional).
On actions 1. and 2., reception remains disabled until the receiver is activated again.
After this is done, and generally in cases 3. and 4., the receiver returns to the (non-
synchronized) Hunt state. In case 5. a HUNT command has to be issued. Reception of
data is internally disabled until synchronization is regained.
Note: Further checking of frame length, extraction of text or data information and
4.5.3
Transmission of data provided in the memory is started after the Transmit Frame (’XF’)
command is issued (the LSB is sent out first). Additionally, the CTS signal may be used
to control data transmission. The message frame is assembled by appending all data
characters to the specified SYN character(s) until Transmit Message End condition is
detected (’XME’ command in interrupt mode or, in DMA mode, when the number of
characters specified in
parity information may be added to each character (SYN, CRC and Preamble characters
are excluded).
If enabled via CRC Append bit (bit ’CAPP’ in register
CRC checksum (16 bit) is added to the message frame. Selection between CRC-16 and
CRC-CCITT algorithms is provided.
Note: - Internally generated SYN characters are always excluded from CRC calculation,
The internal CRC generator is automatically initialized before transmission of a new
frame starts. The initialization value is selectable.
After finishing data transmission, interframe-time-fill (SYN characters or IDLE) is
automatically sent.
A transmit data underrun condition in the XFIFO is indicated with an ’XDU’ interrupt.
Nevertheless, transmission continues inserting SYN characters into the data stream until
Data Sheet
or
verifying the Frame Checking Sequence (e.g. CRC) has to be done by the
microprocessor.
- CRC checksum (2 bytes) is sent without parity.
Data Transmission
XBC1L/XBC1H
have been transferred). Internally generated
108
CCR2H
Detailed Protocol Description
), the internally calculated
PEB 20542
PEF 20542
2000-09-14
CCR1H
),