PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 27

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

1.4
This chapter is useful for all being familiar with the ESCC family.
1.4.1
The SEROCCO-D SCC cores contain the core logic of the ESCC as the heart of the
device. Some enhancements are incorporated in the SCCs. These are:
• Integrated four-channel DMA controller
• Octet-, Bit Synchronous and Asynchronous PPP protocol support as in RFC-1662
• Signaling System #7 (SS7) support
• 4-kByte packet length byte counter
• Enhanced address filtering (16-bit maskable)
• Enhanced time slot assigner
• Support of high data rates (16 Mbit/s)
1.4.2
The following features of the ESCC core have been removed:
• Extended transparent mode 0
• Support of interrupt acknowledge cycles
• Multiplexed address/data bus in Infineon/Intel mode
• Master clock mode
Data Sheet
(this mode provided octet buffered data reception without usage of FIFOs;
SEROCCO-D supports octet buffered reception via appropriate threshold
configurations for the SCC receive FIFOs)
Differences between SEROCCO-D and the ESCC Family
Enhancements to the ESCC Serial Core
Simplifications to the ESCC Serial Core
27
Introduction
PEB 20542
PEF 20542
2000-09-14