PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 43

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

3
The functional blocks of SEROCCO-D can be divided into two major domains:
– the microprocessor interface of SEROCCO-D provides access to on-chip registers
– the Serial Communication Controller (SCC) is capable of processing bit-synchronous
Data exchange between the serial communication controller and the microprocessor
interface is performed using FIFOs, decoupling these two domains.
3.1
Figure 7
Data Sheet
and to the "user" portion of the receive and transmit FIFOs (RFIFO/XFIFO). Optionally
these FIFOs can be accessed by the built-in 4-channel DMA controller.
(HDLC/SDLC/bitsync PPP) and octet-synchronous (octet-sync PPP) as well as fully
transparent data traffic.
55
Functional Overview
Block Diagram
Block Diagram
JTAG Test
Interface
5
(32 Byte)
(32 Byte)
(32 Byte)
(32 Byte)
XFIFO
RFIFO
XFIFO
RFIFO
Serial
Channel A
Serial
Channel B
(32 Byte)
(32 Byte)
43
FIFO
FIFO
HDLC, ASYNC,
PPP, BISYNC
Transmit
LAP D/B
Machine
Machine
Protocol
Receive
Protocol
SS7
TSA
Functional Overview
Decoder/
Collision
Detection
DPLL
Clock
Control
Oscillator
BRG
PEB 20542
PEF 20542
2000-09-14
7
7