PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 80

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

RxD) are connected, generating a local loopback. As a result, the user can perform a
self-test of the SCC.
Figure 35
Transmit data can be disconnected from pin TxD by setting bit TLPO in register CCR2L.
Note: A sufficient clock mode must be used for test loop operation such that receiver and
3.3
The communication between the CPU and SEROCCO-D is done via a set of directly
accessible registers. The interface may be configured as Intel or Motorola type (refer to
description of pin ’BM’) with a selectable data bus width of 8 or 16 bit (refer to description
of pin ’WIDTH’).
The CPU transfers data to/from SEROCCO-D (via 64 byte deep FIFOs per direction and
channel), sets the operating modes, controls function sequences, and gets status
information by writing or reading control/status registers.
All accesses can be done as byte or word accesses if enabled. If 16-bit bus width is
selected, access to the lower/upper part of the data bus is determined by signals BHE/
BLE as shown in
UDS/LDS as shown in
Table 10
BHE
0
0
Data Sheet
transmitter operate with the same frequencies depending on the clock supply (e.g.
clock mode 2b or 6b).
BLE
0
1
Microprocessor Interface
SCC Test Loop
Data Bus Access 16-bit Intel Mode
Register Access
Word access (16 bit)
Byte access (8 bit), odd address
Table 10
SCC transmit
SCC receive
logic
logic
Table 11
(Intel mode) or by the upper and lower data strobe signals
(Motorola mode).
TLP='0'
TLP='1'
IDLE '1'
80
TLPO='0'
TLPO='1'
TxD
Functional Overview
Data Pins Used
D(15:0)
D(15:8)
RxD
PEB 20542
PEF 20542
2000-09-14