PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 252

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

Data Sheet
RE
RMBS(11:0) Receive Maximum Buffer Size
Receive DMA Enable
Only valid in internal DMA controller modes.
Self-clearing command bit:
RE=’0’
RE=’1’
Only valid in internal DMA controller modes.
This bit field determines the reserved size (0..4095 byte) for a receive
buffer in memory. With the base address RBADDRi(23:0), the location
of the receive buffer is defined.
The DMA controller is not set up to forward receive data
into a buffer in memory.
If this bit is set to ’1’, the DMA controller is activated for
transferring receive data into a buffer in memory. This
buffer in memory has to be set up with a valid base
address RBADDRi(23:0) and the maximum buffer size
RMBS(11:0) in advance.
252
Register Description
PEB 20542
PEF 20542
2000-09-14