PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 175

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

Data Sheet
PAR(1:0)
DRCRC
RCRC
PARE
Parity Format
This bit field selects the parity generation/checking mode:
PAR = ’00’
PAR = ’01’
PAR = ’10’
PAR = ’11’
The received parity bit is stored in the SCC receive FIFO depending on
the selected character format:
• as leading bit immediately preceding the data bits if character length
• as LSB of the status byte belonging to the character if character length
A parity error is indicated in the MSB of the status byte belonging to each
character if enabled. In addition, a parity error interrupt can be
generated.
Disable Receive CRC Checking
DRCRC=’0’
DRCRC=’1’
Receive CRC Checking Mode
RCRC=’0’
RCRC=’1’
Parity Enable
PARE=’0’
PARE=’1’
is 5, 6 or 7 bits and bit ’DPS’ is cleared (’0’).
is 8 bits and the corresponding receive FIFO data format is selected
(bit ’RFDF’ = ’1’).
SPACE (’0’), a constant ’0’ is inserted as parity bit.
Odd parity.
Even parity.
MARK (’1’), a constant ’1’ is inserted as parity bit.
The receiver expects a 16 or 32 bit CRC within a HDLC
frame. CRC processing depends on the setting of bit
’RCRC’.
Frames shorter than expected are marked ’invalid’ or are
discarded (refer to
The receiver does not expect any CRC within a HDLC
frame. The criteria for ’valid frame’ indication is updated
accordingly (refer to
Bit ’RCRC’ is ignored.
The received checksum is evaluated, but NOT forwarded
to the receive FIFO.
The received checksum (2 or 4 bytes) is evaluated and
forwarded to the receive FIFO as data.
Parity generation/checking is disabled.
Parity generation/checking is enabled.
5-175
RSTA
RSTA
Register Description (CCR3H)
description).
description).
(async/bisync modes)
(async/bisync modes)
PEB 20542
PEF 20542
(hdlc mode)
(hdlc mode)
2000-09-14