PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 18

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

PEB 20542
PEF 20542
Introduction
1
Introduction
The SEROCCO-D is a DMA Integrated Serial Communication Controller with two
1)
independent serial channels
. The serial channels are derived from updated protocol
logic of the ESCC and DSCC4 device family providing a large set of protocol support and
variety in serial interface configuration. This allows easy integration to different
environments and applications.
A generic 8- or 16-bit demultiplexed master/slave interface provides fast device access
with low bus utilization and easy software handshaking. The internal DMA controller is
optimized for a minimum CPU intervention. Different control mechanisms allow easy
software development well adapted to the needs of special applications (e.g. frame/
packet oriented and continuous transmission/reception).
Large on-chip FIFOs of 64 byte capacity per port and direction in combination with
enhanced threshold control mechanisms allow decoupling of traffic requirements on host
bus and serial interfaces with little exception probabilities such as data underruns or
overflows.
Each of the two Serial Communication Controllers (SCC) contains an independent Baud
Rate Generator, DPLL and programmable protocol processing (HDLC, PPP, ASYNC
and BISYNC). Data rates of up to 16 Mbit/s (HDLC, PPP, bit transparent) and 2 Mbit/s
(DPLL assisted modes) are supported. The channels can also handle a large set of
layer-2 protocol functions (LAPD, SS7) reducing bus and host CPU load. Two channel
specific timers are provided to support protocol functions.
1)
The serial channels are also called ’ports’ or ’cores’ depending on the context.
Data Sheet
18
2000-09-14