PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 59
PEB 20542 F V1.3
Manufacturer Part Number
PEB 20542 F V1.3
Description
IC CTRLR DMA SERIAL 2-CH TQFP144
Manufacturer
Infineon Technologies
Series
SEROCCO™r
Datasheet
1.PEB_20542_F_V1.3.pdf
(300 pages)
Specifications of PEB 20542 F V1.3
Function
Serial Optimized Communications Controller
Interface
HDLC, PPP
Number Of Circuits
2
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
50mA
Power (watts)
150mW
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
144-LFQFP
Includes
Bit Processor Functions, Serial Communication Controllers (SCCs)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB20542FV1.3X
SP000007633
SP000007633
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Note: If time-slot 0 is to be selected, the DELAY has to be as long as the PCM frame
Note: In extended transparent mode the width xCC of the selected time-slot has to be
Data Sheet
itself to achieve synchronization (at least for the 2nd and subsequent PCM
frames): DELAY = PCM frame length = 1 + xTSN*8 + xCS. xTSN and xCS have
to be set appropriately.
Example: Time-slot 0 in E1 (2.048 Mbit/s) system has to be selected.
PCM frame length is 256 clocks. 256 = 1+ xTSN*8 + xCS. => xTSN = 31, xCS = 7.
n ´ 8 bit because of character synchronization (byte alignment). In all other modes
the width can be used to define windows down to a minimum length of one bit.
59
Functional Overview
PEB 20542
PEF 20542
2000-09-14
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