SCC68681E1A44,512 NXP Semiconductors, SCC68681E1A44,512 Datasheet - Page 17

• Manufacturer Part Number: SCC68681E1A44,512
• Description: IC DUART 44PLCC
• Manufacturer: NXP Semiconductors

Specifications of SCC68681E1A44,512

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 3Bit
• Voltage - Supply: 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935274496512; SCC68681E1A44; SCC68681E1A44

square wave with a period of twice the value (in clock periods) of the
the C/T runs continuously. Receipt of a start counter command (read
Philips Semiconductors
receive FIFO and the transfer caused the Channel A FIFO to
become full; i.e., all three FIFO positions are occupied. It is reset
when the CPU reads the RHR. If a character is waiting in the
receive shift register because the FIFO is full, the bit will be set
again when the ISR[0] and IMR waiting character is loaded into the
FIFO.
ISR[0] – Channel A Transmitter Ready
This bit is a duplicate of TxRDYA (SRA[2]).
IMR – Interrupt Mask Register
The programming of this register selects which bits in the ISR
causes an interrupt output. If a bit in the ISR is a ‘1’ and the
corresponding bit in the IMR is also a ‘1’ the INTRN output will be
asserted. If the corresponding bit in the IMR is a zero, the state of
the bit in the ISR has no effect on the INTRN output. Note that the
IMR does not mask the programmable interrupt outputs OP3–OP7
or the reading of the ISR.
CTUR and CTLR – Counter/Timer Registers
The CTUR and CTLR hold the eight MSBs and eight LSBs,
respectively, of the value to be used by the counter/timer in either
the counter or timer modes of operation. The minimum value which
may be loaded into the CTUR/CTLR registers is 0x0002. Note that
these registers are write-only and cannot be read by the CPU.
In the timer (programmable divider) mode, the CT generates a
CTUR and CTLR.
If the value in CTUR and CTLR is changed, the current half-period
will not be affected, but subsequent half periods will be. In this mode
with A3-A0 = 1110) causes the counter to terminate the current
timing cycle and to begin a new cycle using the values in CTUR and
CTLR. The waveform so generated is often used for a data clock.
The formula for calculating the divisor n to load to the CTUR and
CTLR for a particular 1 data clock is shown below:
Often this division will result in a non-integer number; 26.3, for
example. One can only program integer numbers in a digital divider.
Therefore, 26 would be chosen. This gives a baud rate error of
2004 Apr 06
Dual asynchronous receiver/transmitter (DUART)
n
16
counter clock frequency
2
baud rate desired
17
continues counting past the terminal count until stopped by the CPU.
initialization, the output port (OP3) should be masked off through the
may change the values of CTUR and CTLR at any time, but the new
prevent potential problems which may occur if a carry from the lower
0.3/26.3 which is 1.14%; well within the ability asynchronous mode
of operation.
The counter ready status bit (ISR[3]) is set once each cycle of the
square wave. The bit is reset by a stop counter command (read with
A3-A0 = 1111). The command however, does not stop the C/T. The
generated square wave is output on OP3 if it is programmed to be
the C/T output.
On power up and after reset, the timer/counter runs in timer mode
and can only be restarted. Because it cannot be shut off or stopped,
and runs continuously in timer mode, it is recommended that at
OPCR[3:2] = 00 until the T/C is programmed to the desired
operational state.
In the counter mode, the C/T counts down the number of pulses
loaded into CTUR and CTLR by the CPU. Counting begins upon
receipt of a counter command. Upon reaching terminal count
(0x0000), the counter ready interrupt bit (ISR[3]) is set. The counter
If OP3 is programmed to be the output of the C/T, the output
remains HIGH until terminal count is reached, at which time it goes
LOW. The output returns to the HIGH state and ISR[3] is cleared
when the counter is stopped by a stop counter command. The CPU
count becomes effective only on the next start counter command. If
new values have not been loaded, the previous count values are
preserved and used for the next count cycle.
In the counter mode, the current value of the upper and lower 8 bits
of the counter (CTU, CTL) may be read by the CPU.
It is recommended that the counter be stopped when reading to
8 bits to the upper 8 bits occurs between the times that both halves
of the counter are read. However, note that a subsequent start
counter command will cause the counter to begin a new count cycle
using the values in CTUR and CTLR.
IVR – Interrupt Vector Register
This register contains the interrupt vector. The register is initialized
to H‘0F’ by RESET. The contents of the register are placed on the
data bus when the DUART responds to a valid interrupt
acknowledge cycle.
SCC68681
Product data