SCC68681E1A44,512 NXP Semiconductors, SCC68681E1A44,512 Datasheet - Page 3

• Manufacturer Part Number: SCC68681E1A44,512
• Description: IC DUART 44PLCC
• Manufacturer: NXP Semiconductors

Specifications of SCC68681E1A44,512

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 3Bit
• Voltage - Supply: 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935274496512; SCC68681E1A44; SCC68681E1A44

Philips Semiconductors
PIN CONFIGURATIONS
PIN DESCRIPTION
2004 Apr 06
SYMBOL
D0–D7
CSN
R/WN
A1–A4
RESETN
DTACKN
INTRN
IACKN
Dual asynchronous receiver/transmitter (DUART)
PLCC44
2, 4, 6, 7
28, 18,
27, 19,
26, 20,
25, 21
39
38
10
24
41
9
PIN
1, 3, 5, 6
25, 16,
24, 17,
23, 18,
DIP40
22, 19
DTACKN
35
34
21
37
8
9
R/WN
RxDB
TxDB
GND
OP1
OP3
OP5
OP7
IP3
IP1
IP0
A1
A2
A3
A4
D1
D3
D5
D7
18
20
10
11
12
13
14
15
16
17
19
1
2
3
4
5
6
7
8
9
TYPE
I/O
O
O
I
I
I
I
I
DIP
Read/Write: A HIGH input indicates a read cycle and a LOW input indicates a write cycle, when a
IVR to hex 0F, puts OP0–OP7 in the HIGH state, stops the counter/timer, and puts Channel A and
Data Bus: Bidirectional 3-State data bus used to transfer commands, data and status between
the DUART and the CPU. D0 is the least significant bit.
Chip Select: Active-LOW input signal. When LOW, data transfers between the CPU and the
DUART are enabled on D0–D7 as controlled by the R/WN, RDN and A1–A4 inputs. When HIGH,
places the D0–D7 lines in the 3-State condition.
cycle is initiated by assertion of the CSN input.
Address Inputs: Select the DUART internal registers and ports for read/write operations.
Reset: A LOW level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), initializes the
B in the inactive state, with the TxDA and TxDB outputs in the mark (HIGH) state. Clears Test
modes, sets MR pointer to MR1.
Data Transfer Acknowledge: Three-state active LOW output asserted in write, read, or interrupt
cycles to indicate proper transfer of data between the CPU and the DUART.
Interrupt Request: Active-LOW, open-drain, output which signals the CPU that one or more of
the eight maskable interrupting conditions are true.
Interrupt Acknowledge: Active-LOW input indicating an interrupt acknowledge cycle. In
response, the DUART will place the interrupt vector on the data bus and will assert DTACKN if it
has an interrupt pending.
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
IP4
IP5
IACKN
IP2
CSN
RESETN
X2
X1/CLK
RxDA
TxDA
OP0
OP2
OP4
OP6
D0
D2
D4
D6
INTRN
CC
Figure 1. Pin Configurations
3
NAME AND FUNCTION
10 DTACKN
11 RxDB
12 NC
13 TxDB
14 OP1
15 OP3
1
2
3
4
5
6
7
8
9
NC
A1
IP3
A2
IP1
A3
A4
IP0
R/WN
17
7
18
6
PIN/FUNCTION
16 OP5
17 OP7
18 D1
19 D3
20 D5
21 D7
22 GND
23 NC
24 INTRN
25 D6
26 D4
27 D2
28 D0
29 OP6
30 OP4
PLCC
1
40
28
SD00107
31 OP2
32 OP0
33 TxDA
34 NC
35 RxDA
36 X1/CLK
37 X2
38 RESETN
39 CSN
40 IP2
41 IACKN
42 IP5
43 IP4
44 V
39
29
CC
SCC68681
Product data