SCC68681E1A44,512 NXP Semiconductors, SCC68681E1A44,512 Datasheet - Page 8

• Manufacturer Part Number: SCC68681E1A44,512
• Description: IC DUART 44PLCC
• Manufacturer: NXP Semiconductors

Specifications of SCC68681E1A44,512

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 3Bit
• Voltage - Supply: 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935274496512; SCC68681E1A44; SCC68681E1A44

a disable will cause the receiver to begin assembling characters at the
remains valid until overwritten by another received character. Because
Philips Semiconductors
re-asserted (set to ‘0’) automatically. This feature can be used to
prevent an overrun, in the receiver, by connecting the RTSN output
to the CTSN input of the transmitting device.
Receiver Reset and Disable
Receiver disable stops the receiver immediately – data being
assembled if the receiver shift register is lost. Data and status in the
FIFO is preserved and may be read. A re-enable of the receiver after
next start bit detected. A receiver reset will discard the present shift
register data, reset the receiver ready bit (RxRDY), clear the status of
the byte at the top of the FIFO and re-align the FIFO read/write
pointers. This has the appearance of ‘clearing or flushing’ the receiver
FIFO. In fact, the FIFO is NEVER cleared! The data in the FIFO
of this, erroneous reading or extra reads of the receiver FIFO will
mis-align the FIFO pointers and result in the reading of previously
read data. A receiver reset will re-align the pointers.
Multidrop Mode
The DUART is equipped with a wake up mode for multidrop
applications. This mode is selected by programming bits MR1A[4:3] or
MR1B[4:3] to ‘11’ for Channels A and B, respectively. In this mode of
operation, a ‘master’ station transmits an address character followed by
data characters for the addressed ‘slave’ station. The slave stations, with
receivers that are normally disabled, examine the received data stream
and ‘wake up’ the CPU (by setting RxRDY) only upon receipt of an
address character. The CPU compares the received address to its
station address and enables the receiver if it wishes to receive the
subsequent data characters. Upon receipt of another address character,
the CPU may disable the receiver to initiate the process again.
A transmitted character consists of a start bit, the programmed
number of data bits, and Address/Data (A/D) bit, and the
programmed number of stop bits. The polarity of the transmitted A/D
bit is selected by the CPU by programming bit MR1A[2]/MR1B[2].
MR1A[2]/MR1B[2] = 0 transmits a zero in the A/D bit position, which
identifies the corresponding data bits as data while
MR1A[2]/MR1B[2] = 1 transmits a one in the A/D bit position, which
identifies the corresponding data bits as an address. The CPU
should program the mode register prior to loading the corresponding
data bits into the THR.
Table 1.
* See Table 6 for BRG Test frequencies in this data sheet, and “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,
SCC68681 and SCC2698B” in application notes elsewhere in this publication
2004 Apr 06
Dual asynchronous receiver/transmitter (DUART)
A4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SCC68681 Register Addressing
A3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Mode Register A (MR1A, MR2A)
Status Register A (SRA)
BRG Test
Rx Holding Register A (RHRA)
Input Port Change Register (IPCR)
Interrupt Status Register (ISR)
Counter/Timer Upper Value (CTU)
Counter/Timer Lower Value (CTL)
Mode Register B (MR1B, MR2B)
Status Register B (SRB)
1 /16 Test
Rx Holding Register B (RHRB)
Interrupt Vector Register (IVR)
Input Ports IP0 to IP6
Start Counter Command
Stop Counter Command
READ (R/WN = 1)
8
The operation of the DUART is programmed by writing control words
break detect operate normally whether or not the receive is enabled.
In this mode, the receiver continuously looks at the received data
stream, whether it is enabled or disabled. If disabled, it sets the
RxRDY status bit and loads the character into the RHR FIFO if the
received A/D bit is a one (address tag), but discards the received
character if the received A/D bit is a zero (data tag). If enabled, all
received characters are transferred to the CPU via the RHR. In
either case, the data bits are loaded into the data FIFO while the
A/D bit is loaded into the status FIFO position normally used for
parity error (SRA[5] or SRB[5]). Framing error, overrun error, and
PROGRAMMING
into the appropriate registers. Operational feedback is provided via
status registers which can be read by the CPU. The addressing of
the registers is described in Table 1.
The contents of certain control registers are initialized to zero on
RESETN. Care should be exercised if the contents of a register are
changed during operation, since certain changes may cause
operational problems.
For example, changing the number of bits per character while the
transmitter is active may cause the transmission of an incorrect
character. In general, the contents of the MR, the CSR, and the
OPCR should only be changed while the receiver(s) and
transmitter(s) are not enabled, and certain changes to the ACR
should only be made while the C/T is stopped.
Mode registers 1 and 2 of each channel are accessed via
independent auxiliary pointers. The pointer is set to MR1x by RESET
or by issuing a ‘reset pointer’ command via the corresponding
command register. Any read or write of the mode register while the
pointer is at MR1x, switches the pointer to MR2x. The pointer then
remains at MR2x, so that subsequent accesses are always to MR2x
unless the pointer is reset to MR1x as described above.
Mode, command, clock select, and status registers are duplicated
for each channel to provide total independent operation and control.
Refer to Table 2 for register bit descriptions.
Mode Register A (MR1A, MR2A)
Clock Select Register A (CSRA)
Command Register A (CRA)
Tx Holding Register A (THRA)
Aux. Control Register (ACR)
Interrupt Mask Register (IMR)
C/T Upper Preset Value (CRUR)
C/T Lower Preset Value (CTLR)
Mode Register B (MR1B, MR2B)
Clock Select Register B (CSRB)
Command Register B (CRB)
Tx Holding Register B (THRB)
Interrupt Vector Register (IVR)
Output Port Conf. Register (OPCR)
Set Output Port Bits Command
Reset Output Port Bits Command
WRITE (R/WN = 0)
SCC68681
Product data