SCC68681E1A44,512 NXP Semiconductors, SCC68681E1A44,512 Datasheet - Page 7

• Manufacturer Part Number: SCC68681E1A44,512
• Description: IC DUART 44PLCC
• Manufacturer: NXP Semiconductors

Specifications of SCC68681E1A44,512

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 3Bit
• Voltage - Supply: 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935274496512; SCC68681E1A44; SCC68681E1A44

they will be switched to an open drain configuration in which case an
then asserted again which means one full character time of buffering
The SCC68681 is conditioned to receive data when enabled through
Philips Semiconductors
address 0xF with the accompanying data specifying the bits to be
reset (1 = reset, 0 = no change).
Outputs can be also individually assigned specific functions by
appropriate programming of the Channel A mode registers (MR1A,
MR2A), the Channel B mode registers (MR1B, MR2B), and the
Output Port Configuration Register (OPCR).
Please note that these pins drive both HIGH and LOW. However,
when they are programmed to represent interrupt type functions
(such as receiver ready, transmitter ready or counter/timer ready)
external pull-up device would be required.
OPERATION
Transmitter
The SCC68681 is conditioned to transmit data when the transmitter
is enabled through the command register. The SCC68681 indicates
to the CPU that it is ready to accept a character by setting the
TxRDY bit in the status register. This condition can be programmed
to generate an interrupt request at OP6 or OP7 and INTRN. When a
character is loaded into the Transmit Holding Register (THR), the
above conditions are negated. Data is transferred from the holding
register to transmit shift register when it is idle or has completed
transmission of the previous character. The TxRDY conditions are
is provided. Characters cannot be loaded into the THR while the
transmitter is disabled.
The transmitter converts the parallel data from the CPU to a serial
bit stream on the TxD output pin. It automatically sends a start bit
followed by the programmed number of data bits, an optional parity
bit, and the programmed number of stop bits. The least significant
bit is sent first. Following the transmission of the stop bits, if a new
character is not available in the THR, the TxD output remains HIGH
and the TxEMT bit in the Status Register (SR) will be set to 1.
Transmission resumes and the TxEMT bit is cleared when the CPU
loads a new character into the THR.
If the transmitter is disabled, it continues operating until the
character currently being transmitted is completely sent out. The
transmitter can be forced to send a continuous LOW condition by
issuing a send break command.
The transmitter can be reset through a software command (0x30).
If it is reset, operation ceases immediately and the transmitter must
be enabled through the command register before resuming
operation. If CTS operation is enable, the CTSN input must be LOW
in order for the character to be transmitted. If it goes HIGH in the
middle of a transmission, the character in the shift register is
transmitted and TxDA then remains in the marking state until CTSN
goes LOW. The transmitter can also control the deactivation of the
RTSN output. If programmed, the RTSN output will be reset one bit
time after the character in the transmit shift register and transmit
holding register (if any) are completely transmitted, if the transmitter
has been disabled.
Receiver
the command register. The receiver looks for a HIGH-to-LOW
(mark-to-space) transition of the start bit on the RxD input pin. If a
transition is detected, the state of the RxD pin is sampled each 16
clock for 7-
the bit time clock (1 clock mode). If RxD is sampled HIGH, the start
bit is invalid and the search for a valid start bit begins again. If RxD
is still LOW, a valid start bit is assumed and the receiver continues
2004 Apr 06
Dual asynchronous receiver/transmitter (DUART)
1
/
2
clocks (16 clock mode) or at the next rising edge of
7
register into the top most empty position of the FIFO. The RxRDY bit
error, and received break) are also appended to each data character
In the ‘block’ mode, the status provided in the SR for these three bits
contents of the FIFO are not affected; the character previously in the
to sample the input at one bit time intervals at the theoretical center
of the bit, until the proper number of data bits and parity bit (if any)
have been assembled, and one stop bit has been detected. The
least significant bit is received first. The data is then transferred to
the Receive Holding Register (RHR) and the RxRDY bit in the SR is
set to a ‘1’. This condition can be programmed to generate an
interrupt at OP4 or OP5 and INTRN. If the character length is less
than 8 bits, the most significant unused bits in the RHR are set to
zero.
After the stop bit is detected, the receiver will immediately look for
the next start bit. However, if a non-zero character was received
without a stop bit (framing error) and RxD remains LOW for one half
of the bit period after the stop bit was sampled, then the receiver
operates as if a new start bit transition had been detected at that
point (one-half bit time after the stop bit was sampled).
The parity error, framing error, and overrun error (if any) are strobed
into the SR at the received character boundary, before the RxRDY
status bit is set. If a break condition is detected (RxD is LOW for the
entire character including the stop bit), a character consisting of all
zeros will be loaded into the RHR and the received break bit in the
SR is set to ‘1’. The RxD input must return to HIGH for two (2) clock
edges of the X1 crystal clock for the receiver to recognize the end of
the break condition and begin the search for a start bit. This will
usually require a HIGH time of one X1 clock period or 3 X1
edges since the clock of the controller is not synchronous to
the X1 clock.
Receiver FIFO
The RHR consists of a First-In-First-Out (FIFO) stack with a
capacity of three characters. Data is loaded from the receive shift
in the status register is set whenever one or more characters are
available to be read, and a FFULL status bit is set if all three stack
positions are filled with data. Either of these bits can be selected to
cause an interrupt. A read of the RHR outputs the data at the top of
the FIFO. After the read cycle, the data FIFO and its associated
status bits (see below) are ‘popped’ thus emptying a FIFO position
for new data.
Receiver Status Bits
In addition to the data word, three status bits (parity error, framing
in the FIFO (overrun is not). Status can be provided in two ways, as
programmed by the error mode control bit in the mode register. In
the ‘character’ mode, status is provided on a character-by-character
basis; the status applies only to the character at the top of the FIFO.
is the logical-OR of the status for all characters coming to the top of
the FIFO since the last ‘reset error’ command was issued. In either
mode reading the SR does not affect the FIFO. The FIFO is
‘popped’ only when the RHR is read. Therefore the status register
should be read prior to reading the FIFO.
If the FIFO is full when a new character is received, that character is
held in the receive shift register until a FIFO position is available. If
an additional character is received while this state exits, the
shift register is lost and the overrun error status bit (SR[4]) will be
set upon receipt of the start bit of the new (overrunning) character).
The receiver can control the deactivation of RTS. If programmed to
operate in this mode, the RTSN output will be negated (set to ‘1’)
when a valid start bit was received and the FIFO is full. When a
FIFO position becomes available, the RTSN output will be
SCC68681
Product data