STM32F105V8

Manufacturer Part NumberSTM32F105V8
DescriptionMainstream Connectivity line, ARM Cortex-M3 MCU with 64 Kbytes Flash, 72 MHz CPU, CAN, USB 2.0 OTG
ManufacturerSTMicroelectronics
STM32F105V8 datasheet
 


Specifications of STM32F105V8

CoreARM 32-bit Cortex™-M3 CPUConversion Range0 to 3.6 V
Dma12-channel DMA controllerSupported Peripheralstimers, ADCs, DAC, I2Ss, SPIs, I2Cs and USARTs
Systick Timera 24-bit downcounter10/100 Ethernet Mac With Dedicated Dma And Sram (4 Kbytes)IEEE1588 hardware support, MII/RMII available on all packages
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Connectivity line, ARM-based 32-bit MCU with 64/256 KB Flash, USB
OTG, Ethernet, 10 timers, 2 CANs, 2 ADCs, 14 communication interfaces
Features
Core: ARM 32-bit Cortex™-M3 CPU
– 72 MHz maximum frequency,
1.25 DMIPS/MHz (Dhrystone 2.1)
performance at 0 wait state memory
access
– Single-cycle multiplication and hardware
division
Memories
– 64 to 256 Kbytes of Flash memory
– 64 Kbytes of general-purpose SRAM
Clock, reset and supply management
– 2.0 to 3.6 V application supply and I/Os
– POR, PDR, and programmable voltage
detector (PVD)
– 3-to-25 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC with calibration
– 32 kHz oscillator for RTC with calibration
Low power
– Sleep, Stop and Standby modes
– V
supply for RTC and backup registers
BAT
2 × 12-bit, 1 µs A/D converters (16 channels)
– Conversion range: 0 to 3.6 V
– Sample and hold capability
– Temperature sensor
– up to 2 MSPS in interleaved mode
2 × 12-bit D/A converters
DMA: 12-channel DMA controller
– Supported peripherals: timers, ADCs, DAC,
2
2
I
Ss, SPIs, I
Cs and USARTs
Debug mode
– Serial wire debug (SWD) & JTAG interfaces
– Cortex-M3 Embedded Trace Macrocell™
Up to 80 fast I/O ports
– 51/80 I/Os, all mappable on 16 external
interrupt vectors and almost all 5 V-tolerant
CRC calculation unit, 96-bit unique ID
August 2011
LQFP100 14 × 14 mm
LQFP64 10 × 10 mm
Up to 10 timers with pinout remap capability
– Up to four 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input
– 1 × 16-bit motor control PWM timer with
dead-time generation and emergency stop
– 2 × watchdog timers (Independent and
Window)
– SysTick timer: a 24-bit downcounter
– 2 × 16-bit basic timers to drive the DAC
Up to 14 communication interfaces with pinout
remap capability
2
– Up to 2 × I
C interfaces (SMBus/PMBus)
– Up to 5 USARTs (ISO 7816 interface, LIN,
IrDA capability, modem control)
– Up to 3 SPIs (18 Mbit/s), 2 with a
multiplexed I
class accuracy via advanced PLL schemes
– 2 × CAN interfaces (2.0B Active) with
512 bytes of dedicated SRAM
– USB 2.0 full-speed device/host/OTG
controller with on-chip PHY that supports
HNP/SRP/ID with 1.25 Kbytes of dedicated
SRAM
– 10/100 Ethernet MAC with dedicated DMA
and SRAM (4 Kbytes): IEEE1588 hardware
support, MII/RMII available on all packages
Table 1.
Device summary
Reference
STM32F105R8, STM32F105V8
STM32F105xx
STM32F105RB, STM32F105VB
STM32F105RC, STM32F105VC
STM32F107RB, STM32F107VB
STM32F107xx
STM32F107RC, STM32F107VC
Doc ID 15274 Rev 6
STM32F105xx
STM32F107xx
FBGA
LFBGA100 10 × 10 mm
2
S interface that offers audio
Part number
1/103
www.st.com
1

STM32F105V8 Summary of contents

  • Page 1

    ... HNP/SRP/ID with 1.25 Kbytes of dedicated SRAM – 10/100 Ethernet MAC with dedicated DMA and SRAM (4 Kbytes): IEEE1588 hardware support, MII/RMII available on all packages Table 1. Device summary Reference STM32F105R8, STM32F105V8 STM32F105xx STM32F105RB, STM32F105VB STM32F105RC, STM32F105VC STM32F107RB, STM32F107VB STM32F107xx STM32F107RC, STM32F107VC Doc ID 15274 Rev 6 ...

  • Page 2

    Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 3

    STM32F105xx, STM32F107xx 2.3.29 3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 4

    Contents 6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 5

    STM32F105xx, STM32F107xx List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 6

    List of tables Table 45. USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 7

    STM32F105xx, STM32F107xx List of figures Figure 1. STM32F105xx and STM32F107xx connectivity line block diagram . . . . . . . . . . . . . . . . . 12 Figure 2. STM32F105xxx and STM32F107xxx connectivity line BGA100 ...

  • Page 8

    List of figures Figure 44. Recommended footprint Figure 45. LQFP100 P max vs Figure 46. USB OTG FS device mode ...

  • Page 9

    ... STM32F105xx, STM32F107xx 1 Introduction This datasheet provides the description of the STM32F105xx and STM32F107xx connectivity line microcontrollers. For more details on the whole STMicroelectronics STM32F10xxx family, please refer to The STM32F105xx and STM32F107xx datasheet should be read in conjunction with the STM32F10xxx reference manual. For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming manual ...

  • Page 10

    Description 2.1 Device overview Figure 1 shows the general block diagram of the device family. Table 2. STM32F105xx and STM32F107xx features and peripheral counts (1) Peripherals Flash memory in Kbytes SRAM in Kbytes Package Ethernet General-purpose Timers Advanced-control Basic 2 ...

  • Page 11

    STM32F105xx, STM32F107xx 2.2 Full compatibility throughout the family The STM32F105xx and STM32F107xx constitute the connectivity line family whose members are fully pin-to-pin, software and feature compatible. The STM32F105xx and STM32F107xx are a drop-in replacement for the low-density (STM32F103x4/6), medium-density (STM32F103x8/B) ...

  • Page 12

    Description 2.3 Overview Figure 1. STM32F105xx and STM32F107xx connectivity line block diagram TRACECLK TRACED[0:3] TPIU as AF Trace/Trig SW/JTAG NJTRST JTDI JTCK/SWCLK Cortex-M3 CPU JTMS/SWDIO JTDO MHz max NVIC GP DMA1 MII_TXD[3:0]/RMII_TXD[1:0] MII_TX_CLK/RMII_TX_CLK 7 ...

  • Page 13

    STM32F105xx, STM32F107xx ® 2.3.1 ARM Cortex™-M3 core with embedded Flash and SRAM The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of ...

  • Page 14

    Description 2.3.6 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 20 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be ...

  • Page 15

    STM32F105xx, STM32F107xx 2.3.9 Power supply schemes ● 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. DD Provided externally through V ● SSA DDA and PLL (minimum voltage to be applied ...

  • Page 16

    Description ● Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE ...

  • Page 17

    STM32F105xx, STM32F107xx 2.3.15 Timers and watchdogs The STM32F105xx and STM32F107xx devices include an advanced-control timer, four general-purpose timers, two basic timers, two watchdog timers and a SysTick timer. Table 4 compares the features of the general-purpose and basic timers. Table ...

  • Page 18

    Description Any of the standard timers can be used to generate PWM outputs. Each of the timers has independent DMA request generations. Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger generation. They can also be ...

  • Page 19

    STM32F105xx, STM32F107xx USART1, USART2 and USART3 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller except for UART5. 2.3.18 Serial ...

  • Page 20

    Description ● 32-bit CRC generation and removal ● Several address filtering modes for physical and multicast address (multicast and group addresses) ● 32-bit status code for each transmitted or received frame ● Internal FIFOs to buffer transmit and receive frames. ...

  • Page 21

    STM32F105xx, STM32F107xx 2.3.24 Remap capability This feature allows the use of a maximum number of peripherals in a given application. Indeed, alternate functions are available not only on the default pins but also on other specific pins onto which they ...

  • Page 22

    Description Eight DAC trigger inputs are used in the STM32F105xx and STM32F107xx connectivity line family. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels. 2.3.27 Temperature sensor The temperature sensor has ...

  • Page 23

    STM32F105xx, STM32F107xx 3 Pinouts and pin description Figure 2. STM32F105xxx and STM32F107xxx connectivity line BGA100 ballout top view PC14- PC13- A PE2 OSC32_IN TAMPER-RTC PC15 BAT PE3 OSC32_OUT C OSC_IN V SS_5 PE4 D OSC_OUT ...

  • Page 24

    Pinouts and pin description Figure 3. STM32F105xxx and STM32F107xxx connectivity line LQFP100 pinout VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT VSS_5 VDD_5 OSC_IN OSC_OUT NRST VSSA VREF- VREF+ VDDA PA0-WKUP 24/104 PE2 1 PE3 2 PE4 3 PE5 4 PE6 ...

  • Page 25

    STM32F105xx, STM32F107xx Figure 4. STM32F105xxx and STM32F107xxx connectivity line LQFP64 pinout PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT BAT PD0 OSC_IN 5 PD1 ...

  • Page 26

    Pinouts and pin description Table 5. Pin definitions Pins Pin name PE2 PE3 PE4 PE5 PE6 BAT PC13-TAMPER ...

  • Page 27

    STM32F105xx, STM32F107xx Table 5. Pin definitions (continued) Pins Pin name PA2 PA3 SS_4 DD_4 PA4 PA5 PA6 ...

  • Page 28

    Pinouts and pin description Table 5. Pin definitions (continued) Pins Pin name PE13 PE14 PE15 PB10 PB11 SS_1 ...

  • Page 29

    STM32F105xx, STM32F107xx Table 5. Pin definitions (continued) Pins Pin name G10 - 62 PD15 F10 37 63 PC6 E10 38 64 PC7 PC8 PC9 PA8 PA9 D10 43 ...

  • Page 30

    ... This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 8. SPI2/I2S2 and I2C2 are not available when the Ethernet is being used. ...

  • Page 31

    STM32F105xx, STM32F107xx 4 Memory mapping The memory map is shown in Figure 5. Memory map 0xFFFF FFFF 512-Mbyte Cortex-M3's internal 0xE000 0000 peripherals 0xDFFF FFFF 512-Mbyte Not used 0xC000 0000 0xBFFF FFFF 512-Mbyte Not used 0xB000 0000 0xAFFF FFFF 512-Mbyte ...

  • Page 32

    Electrical characteristics 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to V 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply ...

  • Page 33

    STM32F105xx, STM32F107xx 5.1.6 Power supply scheme Figure 8. Power supply scheme 5 × 100 × 4.7 µ µ µF Caution: In Figure 8, the 4.7 µF capacitor must be ...

  • Page 34

    Electrical characteristics 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 7: Current characteristics, and damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. ...

  • Page 35

    STM32F105xx, STM32F107xx Table 8. Thermal characteristics Symbol T STG T J 5.3 Operating conditions 5.3.1 General operating conditions Table 9. General operating conditions Symbol f Internal AHB clock frequency HCLK f Internal APB1 clock frequency PCLK1 f Internal APB2 clock ...

  • Page 36

    Electrical characteristics 5.3.2 Operating conditions at power-up / power-down Subject to general operating conditions for T Table 10. Operating conditions at power-up / power-down Symbol V rise time rate DD t VDD V fall time rate DD 5.3.3 Embedded reset ...

  • Page 37

    STM32F105xx, STM32F107xx 5.3.4 Embedded reference voltage The parameters given in temperature and V Table 12. Embedded internal reference voltage Symbol V Internal reference voltage REFINT ADC sampling time when (1) T reading the internal reference S_vrefint voltage Internal reference voltage ...

  • Page 38

    Electrical characteristics Table 13. Maximum current consumption in Run mode, code with data processing running from Flash Symbol Parameter Supply current Run mode 1. Based on characterization, not tested in production. 2. External clock is 8 MHz ...

  • Page 39

    STM32F105xx, STM32F107xx Table 15. Maximum current consumption in Sleep mode, code running from Flash or RAM Symbol Parameter Supply current Sleep mode 1. Based on characterization, tested in production External clock is 8 MHz ...

  • Page 40

    Electrical characteristics Figure 10. Typical current consumption on V different V Figure 11. Typical current consumption in Stop mode with regulator in Run mode versus temperature at different V 40/104 values BAT 2.5 2 1.5 1 0.5 0 –40 °C ...

  • Page 41

    STM32F105xx, STM32F107xx Figure 12. Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at different V Figure 13. Typical current consumption in Standby mode versus temperature at different V Typical current consumption The MCU is placed ...

  • Page 42

    Electrical characteristics Table 17. Typical current consumption in Run mode, code with data processing running from Flash Symbol Parameter Supply I current in DD Run mode 1. Typical values are measures Add an additional power consumption of ...

  • Page 43

    STM32F105xx, STM32F107xx Table 18. Typical current consumption in Sleep mode, code running from Flash or RAM Symbol Parameter Supply I current in DD Sleep mode 1. Typical values are measures Add an additional power consumption of 0.8 ...

  • Page 44

    Electrical characteristics Table 19. Peripheral current consumption Peripheral AHB APB1 APB2 MHz, f HCLK 2. Specific conditions for ADC the ADC_CR2 register is set to 1. 44/104 Typical consumption at 25 °C ETH_MAC OTG_FS ...

  • Page 45

    STM32F105xx, STM32F107xx 5.3.6 External clock source characteristics High-speed external user clock generated from an external source The characteristics given in external clock source, and under ambient temperature and supply voltage conditions summarized in Table Table 20. High-speed external user clock ...

  • Page 46

    Electrical characteristics Figure 14. High-speed external clock source AC timing diagram V HSEH 90% 10% V HSEL t r(HSE) External clock source Figure 15. Low-speed external clock source AC timing diagram V LSEH 90% 10% V LSEL t r(LSE) External ...

  • Page 47

    STM32F105xx, STM32F107xx Table 22. HSE 3-25 MHz oscillator characteristics Symbol f Oscillator frequency OSC_IN R Feedback resistor F Recommended load capacitance C versus equivalent serial resistance of the crystal (R i HSE driving current 2 g Oscillator transconductance m (4) ...

  • Page 48

    Electrical characteristics resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 23. LSE oscillator characteristics (f Symbol Parameter R Feedback resistor F Recommended load capacitance (2) C versus equivalent serial resistance of the crystal (R I ...

  • Page 49

    STM32F105xx, STM32F107xx Figure 17. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors OSC32_IN Bias 32.768 KH z controlled R F resonator gain OSC32_OU T Doc ID 15274 Rev 6 Electrical characteristics f LSE ...

  • Page 50

    Electrical characteristics 5.3.7 Internal clock source characteristics The parameters given in temperature and V High-speed internal (HSI) RC oscillator Table 24. HSI oscillator characteristics Symbol Parameter f Frequency HSI DuCy Duty cycle (HSI) Accuracy of the HSI ACC HSI oscillator ...

  • Page 51

    STM32F105xx, STM32F107xx All timings are derived from tests performed under ambient temperature and V voltage conditions summarized in Table 26. Low-power mode wakeup timings Symbol (1) t WUSLEEP (1) t WUSTOP (1) t WUSTDBY 1. The wakeup times are measured ...

  • Page 52

    Electrical characteristics 5.3.9 Memory characteristics Flash memory The characteristics are given at T Table 29. Flash memory characteristics Symbol Parameter t 16-bit programming time T prog t Page (1 KB) erase time ERASE t Mass erase time ME I Supply ...

  • Page 53

    STM32F105xx, STM32F107xx Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: ...

  • Page 54

    Electrical characteristics Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with SAE IEC61967-2 standard which specifies the test ...

  • Page 55

    STM32F105xx, STM32F107xx 5.3.12 I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below V above V (for standard, 3 V-capable I/O pins) should be avoided during normal product DD operation. However, ...

  • Page 56

    Electrical characteristics Table 36. I/O static characteristics Symbol Parameter Standard IO Schmitt trigger voltage (2) hysteresis V hys IO FT Schmitt trigger (2) voltage hysteresis (4) I Input leakage current lkg All pins Weak pull- except for up R PA10 ...

  • Page 57

    STM32F105xx, STM32F107xx Figure 19. Standard I/O input characteristics - TTL port Doc ID 15274 Rev 6 Electrical characteristics 57/104 ...

  • Page 58

    Electrical characteristics Figure 20 tolerant I/O input characteristics - CMOS port Figure 21 tolerant I/O input characteristics - TTL port – 58/104 Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx ...

  • Page 59

    STM32F105xx, STM32F107xx Output driving current The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/-20 mA (with a relaxed V In the user application, the number of I/O pins which ...

  • Page 60

    Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Table 38, respectively. Unless otherwise specified, the parameters given in performed under the ambient temperature and V in Table 9. Table 38. I/O AC ...

  • Page 61

    STM32F105xx, STM32F107xx Figure 22. I/O AC characteristics definition EXT ERNAL OUTPUT ON 50pF Maximum frequency is achieved ≤ 2/3)T and if the duty cycle is (45-55%) 5.3.14 NRST pin characteristics The NRST pin ...

  • Page 62

    Electrical characteristics Figure 23. Recommended NRST pin protection External (1) reset circuit 2. The reset network protects the device against parasitic resets. 3. The user must ensure that the level on the NRST pin can go below the V Table ...

  • Page 63

    STM32F105xx, STM32F107xx 5.3.16 Communications interfaces interface characteristics Unless otherwise specified, the parameters given in performed under the ambient temperature, f conditions summarized in The STM32F105xx and STM32F107xx I 2 standard I C communication protocol with the following ...

  • Page 64

    Electrical characteristics 2 Figure 24 bus AC waveforms and measurement circuit I²C bus Start SDA t f(SDA) t h(STA) SCL t w(SCLH) 1. Measurement points are done at CMOS levels: 0.3V Table 42. SCL frequency ( ...

  • Page 65

    STM32F105xx, STM32F107xx SPI interface characteristics Unless otherwise specified, the parameters given in are derived from tests performed under the ambient temperature, f supply voltage conditions summarized in Refer to Section 5.3.12: I/O current injection characteristics input/output ...

  • Page 66

    Electrical characteristics Figure 25. SPI timing diagram - slave mode and CPHA = 0 NSS input t SU(NSS) CPHA= 0 CPOL=0 t w(SCKH) CPHA w(SCKL) CPOL=1 t a(SO) MISO OUT su(SI) MOSI I NPUT Figure ...

  • Page 67

    STM32F105xx, STM32F107xx Figure 27. SPI timing diagram - master mode High NSS input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 t su(MI) MISO INP UT MOSI OUTUT 1. Measurement points are done at CMOS levels: 0.3V (1) ...

  • Page 68

    Electrical characteristics 2 Table 44 characteristics Symbol Parameter clock frequency 1/t c(CK r(CK clock rise and fall time t f(CK) ( clock high time w(CKH) ...

  • Page 69

    STM32F105xx, STM32F107xx 2 Figure 28 slave timing diagram (Philips protocol) CPOL = 0 CPOL = 1 WS input SD transmit SD receive 1. Measurement points are done at CMOS levels: 0.3 × LSB transmit/receive of the ...

  • Page 70

    Electrical characteristics USB OTG FS characteristics The USB OTG interface is USB-IF certified (Full-Speed). Table 45. USB OTG FS startup time Symbol (1) t STARTUP 1. Guaranteed by design, not tested in production. Table 46. USB OTG FS DC electrical ...

  • Page 71

    STM32F105xx, STM32F107xx Table 47. USB OTG FS electrical characteristics Symbol t Rise time r t Fall time f t Rise/ fall time matching rfm V Output signal crossover voltage CRS 1. Guaranteed by design, not tested in production. 2. Measured ...

  • Page 72

    Electrical characteristics Figure 32. Ethernet RMII timing diagram RMII_REF_CLK RMII_TX_EN RMII_TXD[1:0] RMII_RXD[1:0] RMII_CRS_DV Table 50. Dynamic characteristics: Ethernet MAC signals for RMII Symbol t Receive data setup time su(RXD) t Receive data hold time ih(RXD) t Carrier sense set-up time ...

  • Page 73

    STM32F105xx, STM32F107xx Table 51. Dynamic characteristics: Ethernet MAC signals for MII Symbol t Receive data setup time su(RXD) t Receive data hold time ih(RXD) t Data valid setup time su(DV) t Data valid hold time ih(DV) t Error setup time ...

  • Page 74

    Electrical characteristics Table 52. ADC characteristics (continued) Symbol Parameter (2) t Injection trigger conversion latency lat (2) t Regular trigger conversion latency latr (2) t Sampling time S (2) t Power-up time STAB Total conversion time (including (2) t CONV ...

  • Page 75

    STM32F105xx, STM32F107xx Table 54. ADC accuracy - limited test conditions Symbol ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error 1. ADC DC accuracy values are measured after internal calibration. 2. ...

  • Page 76

    Electrical characteristics Figure 34. ADC accuracy characteristics [1LSB = IDEAL 4095 4094 4093 SSA Figure 35. Typical connection diagram using the ADC V AIN 1. Refer to ...

  • Page 77

    STM32F105xx, STM32F107xx General PCB design guidelines Power supply decoupling should be performed as shown in depending on whether V ceramic (good quality). They should be placed them as close as possible to the chip. Figure 36. Power supply and reference ...

  • Page 78

    Electrical characteristics 5.3.18 DAC electrical specifications Table 56. DAC characteristics Symbol Parameter V Analog supply voltage DDA V Reference supply voltage REF+ V Ground SSA (1) R Resistive load with buffer ON LOAD Impedance output with buffer ( ...

  • Page 79

    STM32F105xx, STM32F107xx Table 56. DAC characteristics (continued) Symbol Parameter Offset error (difference between (2) Offset measured value at Code (0x800) and the ideal value = V /2) REF+ Gain Gain error (2) error Settling time (full scale: for a 10-bit ...

  • Page 80

    Electrical characteristics 5.3.19 Temperature sensor characteristics Table 57. TS characteristics Symbol ( SENSE L (1) Avg_Slope Average slope (1) Voltage at 25 ° (2) Startup time t START ADC sampling time when reading the (3)(2) T ...

  • Page 81

    STM32F105xx, STM32F107xx 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status ...

  • Page 82

    Package characteristics Figure 39. LFBGA100 - low profile fine pitch ball grid array package outline Table 58. LFBGA100 - low profile fine pitch ball grid array package mechanical data Dim ...

  • Page 83

    STM32F105xx, STM32F107xx Figure 40. Recommended PCB design rules (0.80/0.75 mm pitch BGA) Dpad Dpad Dsm Solder paste – Non solder mask defined pads are recommended – mils screen print Dsm Doc ID 15274 Rev 6 Package characteristics ...

  • Page 84

    Package characteristics Figure 41. LQFP100, 100-pin low-profile quad flat package outline 100 26 Pin identification e 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 59. LQPF100 ...

  • Page 85

    STM32F105xx, STM32F107xx Figure 43. LQFP64 – 64 pin low-profile quad flat package outline Drawing is not to scale. 2. Dimensions are in millimeters. Table 60. LQFP64 – 64 pin low-profile quad flat package mechanical data ...

  • Page 86

    Package characteristics 6.2 Thermal characteristics The maximum chip junction temperature (T Table 9: General operating conditions on page The maximum chip-junction temperature, T using the following equation: Where: max is the maximum ambient temperature in °C, ● Θ ...

  • Page 87

    STM32F105xx, STM32F107xx 6.2.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to ...

  • Page 88

    Package characteristics Using the values obtained in – For LQFP100, 46 °C 115 °C + (46 °C/W × 134 mW) = 115 °C + 6.2 °C = 121.2 °C Jmax This is within the range of the suffix ...

  • Page 89

    STM32F105xx, STM32F107xx 7 Part numbering Table 62. Ordering information scheme Example: Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 105 = connectivity, USB OTG FS 107= connectivity, USB OTG FS & Ethernet Pin count ...

  • Page 90

    Application block diagrams Appendix A Application block diagrams A.1 USB OTG FS interface solutions Figure 46. USB OTG FS device mode STM32F105xx/STM32F107xx USB OTG Full-speed core 1. Use a regulator if you want to build a bus-powered device. 90/104 OTG ...

  • Page 91

    STM32F105xx, STM32F107xx Figure 47. Host connection STM32F105xx/STM32F107xx USB OTG Full-speed core 1. STMPS2141STR needed only if the application has to support bus-powered devices. OTG PHY USB full-speed/ low-speed transceiver HNP HNP ID ID SRP SRP EN GPIO OVRCR GPIO + ...

  • Page 92

    Application block diagrams Figure 48. OTG connection (any protocol) STM32F105xx/STM32F107xx USB OTG Full-speed core 1. STMPS2141STR needed only if the application has to support bus-powered devices. A.2 Ethernet interface solutions Figure 49. MII mode using a 25 MHz crystal MCU ...

  • Page 93

    STM32F105xx, STM32F107xx Figure 50. RMII with a 50 MHz oscillator MCU HCLK TIM2 OSC 50 MHz 1. HCLK must be greater than 25 MHz. Figure 51. RMII with a 25 MHz crystal and PHY with PLL MCU HCLK TIM2 2.5 ...

  • Page 94

    Application block diagrams Figure 52. RMII with a 25 MHz crystal MCU HCLK TIM2 XTAL OSC 25 MHz 1. The NS DP83848 is recommended as the input jitter requirement of this PHY compliant with the output jitter specification ...

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    STM32F105xx, STM32F107xx A.3 Complete audio player solutions Two solutions are offered, illustrated in Figure 53 shows storage media to audio DAC/amplifier streaming using a software Codec. This solution implements an audio crystal to provide audio class I clock (0.5% error ...

  • Page 96

    Application block diagrams A.4 USB OTG FS interface + Ethernet/I With the clock tree implemented on the STM32F107xx, only one crystal is required to work with both the USB (host/device/OTG) and the Ethernet (MII/RMII) interfaces. illustrate the solution. Figure 55. ...

  • Page 97

    STM32F105xx, STM32F107xx Table 63. PLL configurations Crystal value in Application PREDIV2 PLL2MUL PLLSRC MHz (XT1) Ethernet only 25 /5 Ethernet + OTG 25 /5 Ethernet + OTG basic audio Ethernet + OTG + Audio class 14.7456 /4 ...

  • Page 98

    Application block diagrams Table 64. Applicative current consumption in Run mode, code with data processing running from Flash Symbol parameter Supply current run mode 3 Based on characterization, not tested in ...

  • Page 99

    STM32F105xx, STM32F107xx Revision history Table 65. Document revision history Date 18-Dec-2008 20-Feb-2009 Revision 1 Initial release. I/O information clarified STM32F107xxx connectivity line BGA100 ballout top view Section 2.3.8: Boot modes PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default column to ...

  • Page 100

    Revision history Table 65. Document revision history (continued) Date 19-Jun-2009 100/104 Revision Section 2.3.8: Boot modes interface with dedicated DMA and IEEE 1588 support Section 2.3.24: Remap capability Figure 1: STM32F105xx and STM32F107xx connectivity line block diagram and Figure 5: ...

  • Page 101

    STM32F105xx, STM32F107xx Table 65. Document revision history (continued) Date 14-Sep-2009 Revision Document status promoted from Preliminary data to full datasheet. Number of DACs corrected in STM32F107xx family versus STM32F103xx Note 5 added in Table 5: Pin V and T added ...

  • Page 102

    Revision history Table 65. Document revision history (continued) Date 11-May-2010 01-Aug-2011 102/104 Revision Added BGA package. Table 5: Pin definitions: ETH_RMII_RXD0 and ETH_RMII_RXD1 added in remap column for PD9 and PD10, respectively. Note added to ETH_MII_RX_DV, ETH_MII_RXD0, ETH_MII_RXD1, ETH_MII_RXD2 and ...

  • Page 103

    ... STM32F105xx, STM32F107xx Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...