STM32L162QD STMicroelectronics, STM32L162QD Datasheet - Page 20

• Manufacturer Part Number: STM32L162QD
• Description: Ultra-low-power ARM Cortex-M3 MCU with 384 Kbytes Flash, 32 MHz CPU, LCD, USB, 3xOp-amp, AES
• Manufacturer: STMicroelectronics

Specifications of STM32L162QD

• Operating Power Supply Range: 1.65 V to 3.6 V (without BOR) or 1.8 V to 3.6 V
• 7 Modes: Sleep, Low-power run (11 μA at 32 kHz), Low-power sleep (4.4 μA), Stop with RTC, Stop (650 nA), Standby with RTC, Standby (300 nA)
• Ultralow Leakage Per I/o: 50 nA max
• Fast Wakeup Time From Stop: 8 μs
• Core: ARM 32-bit Cortex™-M3 CPU
• Dma: 12-channel DMA controller
• 11 Timers: one 32-bit and six 16-bit general-purpose timers, two 16-bit basic timers, two watchdog timers (independent and window)

Functional overview
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Memories
The STM32L162xD devices have the following features:
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FSMC (flexible static memory controller)
The FSMC supports the following modes: SRAM, PSRAM, NOR Flash.
Functionality overview:
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DMA (direct memory access)
The flexible 12-channel, general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management, avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with software trigger
support for each channel. Configuration is done by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: AES, SPI, I
purpose timers, DAC, and ADC.
48 Kbyte of embedded RAM accessed (read/write) at CPU clock speed with 0 wait
states. With the enhanced bus matrix, operating the RAM does not lead to any
performance penalty during accesses to the system bus (AHB and APB buses).
The non-volatile memory is divided into three arrays:
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Flash program and data EEPROM are divided into two banks, this enables writing in
one bank while running code or reading data in the other bank.
The options bytes are used to write-protect the memory (with 4 KB granularity) and/or
readout-protect the whole memory with the following options:
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The whole non-volatile memory embeds the error correction code (ECC) feature.
Up to 26 bit address bus
Up to 16-bit data bus
Write FIFO
Burst mode
Code execution from external memory
Four chip select signals
Up to 32 MHz external access (TBC)
384 Kbyte of embedded Flash program memory
12 Kbyte of data EEPROM
Options bytes
Level 0: no readout protection
Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
Level 2: chip readout protection, debug features (Cortex-M3 JTAG and serial wire)
and boot in RAM selection disabled (JTAG fuse)
STM32L162VD, STM32L162ZD, STM32L162QD, STM32L162RD
Doc ID 022268 Rev 2
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C, USART, SDIO, general-