STM32L162QD STMicroelectronics, STM32L162QD Datasheet - Page 97

• Manufacturer Part Number: STM32L162QD
• Description: Ultra-low-power ARM Cortex-M3 MCU with 384 Kbytes Flash, 32 MHz CPU, LCD, USB, 3xOp-amp, AES
• Manufacturer: STMicroelectronics

Specifications of STM32L162QD

• Operating Power Supply Range: 1.65 V to 3.6 V (without BOR) or 1.8 V to 3.6 V
• 7 Modes: Sleep, Low-power run (11 μA at 32 kHz), Low-power sleep (4.4 μA), Stop with RTC, Stop (650 nA), Standby with RTC, Standby (300 nA)
• Ultralow Leakage Per I/o: 50 nA max
• Fast Wakeup Time From Stop: 8 μs
• Core: ARM 32-bit Cortex™-M3 CPU
• Dma: 12-channel DMA controller
• 11 Timers: one 32-bit and six 16-bit general-purpose timers, two 16-bit basic timers, two watchdog timers (independent and window)

STM32L162VD, STM32L162ZD, STM32L162QD, STM32L162RD
SPI characteristics
Unless otherwise specified, the parameters given in the following table are derived from
tests performed under ambient temperature, f
conditions summarized in
Refer to
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 54.
1. Remapped SPI1 characteristics to be determined.
2. Based on characterization, not tested in production.
3. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the
4. Min time is for the minimum time to invalidate the output and max time is for the maximum time to put the
DuCy(SCK)
t
Symbol
1/t
t
t
t
t
t
data.
data in Hi-Z.
t
dis(SO)
t
t
w(SCKH)
v(SO)
t
w(SCKL)
v(MO)
h(MO)
a(SO)
h(SO)
t
t
su(NSS)
t
t
h(NSS)
r(SCK)
f(SCK)
t
su(MI)
t
f
su(SI)
h(MI)
c(SCK)
SCK
h(SI)
(3)
(2)
(2)
(2)
(2)
Section 6.3.12: I/O current injection characteristics
(4)
SPI characteristics
SPI clock frequency
SPI clock rise and fall
time
SPI slave input clock duty
cycle
NSS setup time
NSS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output valid time
Data output hold time
Parameter
Table
Doc ID 022268 Rev 2
10.
(1)
Master mode
Slave mode
Capacitive load: C = 30 pF
Slave mode
Slave mode
Slave mode
Master mode, f
presc = 4
Master mode
Slave mode
Master mode
Slave mode
Slave mode, f
Slave mode
Slave mode (after enable edge)
Master mode (after enable edge)
Slave mode (after enable edge)
Master mode (after enable edge)
PCLKx
Conditions
PCLK
frequency and V
PCLK
= 20 MHz
= 16 MHz,
for more details on the
Electrical characteristics
DD
4t
2t
Min
TBD
TBD
TBD
TBD
supply voltage
PCLK
PCLK
30
5
5
5
4
0
Max
3t
TBD
TBD
TBD
TBD
TBD
PCLK
16
16
70
(2)
97/124
MHz
Unit
ns
ns
%