STM32L162QD STMicroelectronics, STM32L162QD Datasheet - Page 95

• Manufacturer Part Number: STM32L162QD
• Description: Ultra-low-power ARM Cortex-M3 MCU with 384 Kbytes Flash, 32 MHz CPU, LCD, USB, 3xOp-amp, AES
• Manufacturer: STMicroelectronics

Specifications of STM32L162QD

• Operating Power Supply Range: 1.65 V to 3.6 V (without BOR) or 1.8 V to 3.6 V
• 7 Modes: Sleep, Low-power run (11 μA at 32 kHz), Low-power sleep (4.4 μA), Stop with RTC, Stop (650 nA), Standby with RTC, Standby (300 nA)
• Ultralow Leakage Per I/o: 50 nA max
• Fast Wakeup Time From Stop: 8 μs
• Core: ARM 32-bit Cortex™-M3 CPU
• Dma: 12-channel DMA controller
• 11 Timers: one 32-bit and six 16-bit general-purpose timers, two 16-bit basic timers, two watchdog timers (independent and window)

STM32L162VD, STM32L162ZD, STM32L162QD, STM32L162RD
6.3.16
Communications interfaces
I
Unless otherwise specified, the parameters given in
performed under ambient temperature, f
summarized in
The STM32L162xD product line I
communication protocol with the following restrictions: SDA and SCL are not “true” open-
drain I/O pins. When configured as open-drain, the PMOS connected between the I/O pin
and V
The I
injection characteristics
(SDA and SCL) .
Table 52.
1. Guaranteed by design, not tested in production.
2. f
3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
2
t
C interface characteristics
w(STO:STA)
Symbol
t
t
t
t
t
w(SCLH)
w(SCLL)
t
su(SDA)
t
t
su(STO)
to achieve fast mode I²C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I²C
fast mode clock.
period of SCL signal.
undefined region of the falling edge of SCL.
t
t
t
su(STA)
h(SDA)
PCLK1
r(SDA)
h(STA)
r(SCL)
f(SDA)
f(SCL)
C
2
DD
C characteristics are described in
b
must be higher than 2 MHz to achieve standard mode I
is disabled, but is still present.
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
Start condition hold time
Repeated Start condition
setup time
Stop condition setup time
Stop to Start condition time
(bus free)
Capacitive load for each bus
line
I
2
C characteristics
Table
Parameter
10.
for more details on the input/output alternate function characteristics
Doc ID 022268 Rev 2
2
C interface meets the requirements of the standard I
Standard mode I
PCLK1
Table
Min
250
0
4.7
4.0
4.0
4.7
4.0
4.7
(3)
frequency and V
52. Refer also to
²
Table 52
C frequencies. It must be higher than 4 MHz
1000
Max
300
400
2
C
(1)
are derived from tests
20 + 0.1C
DD
Fast mode I
Section 6.3.12: I/O current
Electrical characteristics
Min
100
0
1.3
0.6
0.6
0.6
0.6
1.3
supply voltage conditions
(4)
b
2
C
900
Max
300
300
400
(1)(2)
(3)
95/124
Unit
pF
2
µs
ns
µs
μs
μs
C