ST72324BJ6 STMicroelectronics, ST72324BJ6 Datasheet - Page 105

• Manufacturer Part Number: ST72324BJ6
• Description: 5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324BJ6

• Hdflash Endurance: 1 kcycle at 55 °C, data retention 40 years at 85 °C
• Clock Sources: crystal/ceramic resonator oscillators, int. RC osc. and ext. clock input
• 4 Power Saving Modes: Slow, Wait, Active-halt, and Halt

ST72324Bxx
Table 55.
Table 56.
1:0 SPR[1:0]
Bit
7
6
5
4
3
2
MSTR
Name
CPOL
CPHA
SPR2
SPIE
SPE
SPICR register description
SPI master mode SCK frequency
Serial clock
Serial Peripheral Interrupt Enable
Serial Peripheral Output Enable
Divider Enable
Master mode
Clock Polarity
Clock Phase
Serial clock frequency
This bit is set and cleared by software.
0: Interrupt is inhibited.
1: An SPI interrupt is generated whenever SPIF = 1, MODF = 1 or OVR = 1 in the
SPICSR register.
This bit is set and cleared by software. It is also cleared by hardware when, in
master mode, SS = 0 (see
is cleared by reset, so the SPI peripheral is not initially connected to the external
pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
This bit is set and cleared by software and is cleared by reset. It is used with the
SPR[1:0] bits to set the baud rate. Refer to
frequency.
0: Divider by 2 enabled
1: Divider by 2 disabled
Note: This bit has no effect in slave mode.
This bit is set and cleared by software. It is also cleared by hardware when, in
master mode, SS = 0 (see
0: Slave mode
1: Master mode. The function of the SCK pin changes from an input to an output
and the functions of the MISO and MOSI pins are reversed.
This bit is set and cleared by software. This bit determines the idle state of the
serial Clock. The CPOL bit affects both the master and slave modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Note: If CPOL is changed at the communication byte boundaries, the SPI must be
disabled by resetting the SPE bit.
This bit is set and cleared by software.
0: The first clock transition is the first data capture edge.
1: The second clock transition is the first capture edge.
Note: The slave must have the same CPOL and CPHA settings as the master.
These bits are set and cleared by software. Used with the SPR2 bit, they select
the baud rate of the SPI serial clock SCK output by the SPI in master mode
(seeTable
Note: These 2 bits have no effect in slave mode.
f
f
CPU
CPU
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56).
Master mode fault (MODF) on page
Master mode fault (MODF) on page
SPR2
Function
1
0
Table 56: SPI master mode SCK
SPR1
0
0
On-chip peripherals
102). The SPE bit
102).
SPR0
0
0
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