ST72324BJ6 STMicroelectronics, ST72324BJ6 Datasheet - Page 42

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ST72324BJ6

Manufacturer Part Number
ST72324BJ6
Description
5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST72324BJ6

Hdflash Endurance
1 kcycle at 55 °C, data retention 40 years at 85 °C
Clock Sources
crystal/ceramic resonator oscillators, int. RC osc. and ext. clock input
4 Power Saving Modes
Slow, Wait, Active-halt, and Halt
Interrupts
7.2.1
42/193
Table 14.
Figure 18. Interrupt processing flowchart
Servicing pending interrupts
As several interrupts can be pending at the same time, the interrupt to be taken into account
is determined by the following two-step process:
Figure 19
Figure 19. Priority decision process flowchart
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable)
the highest software priority interrupt is serviced,
if several interrupts have the same software priority then the interrupt with the highest
hardware priority is serviced first.
describes this decision process.
Interrupt software priority
RESTORE PC, X, A, CC
Interrupt software priority levels
Reset
from stack
HIGHEST HARDWARE
PRIORITY SERVICED
Same
Y
Pending
I
instruction
Fetch next
nterrupt
I
nstruction
Execute
N
“IRET”
N
INTERRUPTS
SOFTWARE
PRIORITY
PENDING
HIGHEST SOFTWARE
PRIORITY SERVICED
Y
stays pending
The interrupt
Interrupt has the same or a
Level
Different
High
Low
lower software priority
load I1:0 from interrupt SW reg.
than current one
load PC from interrupt vector
Stack PC, X, A, CC
I1
1
0
0
1
TRAP
I1:0
N
ST72324Bxx
Y
I0
0
1
0
1

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