ST72324BJ6 STMicroelectronics, ST72324BJ6 Datasheet - Page 164

• Manufacturer Part Number: ST72324BJ6
• Description: 5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324BJ6

• Hdflash Endurance: 1 kcycle at 55 °C, data retention 40 years at 85 °C
• Clock Sources: crystal/ceramic resonator oscillators, int. RC osc. and ext. clock input
• 4 Power Saving Modes: Slow, Wait, Active-halt, and Halt

Electrical characteristics
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RESET pin protection when LVD is disabled
When the LVD is disabled, it is recommended to protect the RESET pin as shown in
Figure 79
1.
2.
3.
4.
Figure 79. RESET pin protection when LVD is disabled
The reset network protects the device against parasitic resets.
The output of the external reset circuit must have an open-drain output to drive the ST7
reset pad. Otherwise the device can be damaged when the ST7 generates an internal
reset (LVD or watchdog).
Whatever the reset source is (internal or external), the user must ensure that the level
on the RESET pin can go below the V
Otherwise the reset will not be taken into account internally.
Because the reset circuit is designed to allow the internal RESET to be output in the
RESET pin, the user must ensure that the current sunk on the RESET pin (by an
external pull-up for example) is less than the absolute maximum value specified for
I
INJ(RESET)
Required
external
circuit
User
reset
and follow these guidelines:
in
Section 12.2.2 on page
0.01µF
V
DD
4.7kΩ
V
143.
DD
IL
R
max. level specified in
ON
Filter
generator
Pulse
Section
12.10.1.
Watchdog
ST72324Bxx
ST72XXX
Internal
reset