ST72324BJ6 STMicroelectronics, ST72324BJ6 Datasheet - Page 124

• Manufacturer Part Number: ST72324BJ6
• Description: 5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324BJ6

• Hdflash Endurance: 1 kcycle at 55 °C, data retention 40 years at 85 °C
• Clock Sources: crystal/ceramic resonator oscillators, int. RC osc. and ext. clock input
• 4 Power Saving Modes: Slow, Wait, Active-halt, and Halt

On-chip peripherals
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Table 64.
SCI data register (SCIDR)
This register contains the received or transmitted data character, depending on whether it is
read from or written to.
The Data register performs a double function (read and write) since it is composed of two
registers, one for transmission (TDR) and one for reception (RDR).
The TDR register provides the parallel interface between the internal bus and the output
shift register (see
input shift register and the internal bus (see
SCIDR
Bit
3
2
1
0
DR7
R/W
7
Name
RWU
SBK
RE
TE
SCICR2 register description (continued)
Transmitter enable
Receiver enable
Receiver wakeup
Send break
DR6
R/W
This bit enables the transmitter. It is set and cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
Notes:
- During transmission, a ‘0’ pulse on the TE bit (‘0’ followed by ‘1’) sends a preamble
(Idle line) after the current word.
- When TE is set there is a 1 bit-time delay before the transmission starts.
Caution: The TDO pin is free for general purpose I/O only when the TE and RE bits
are both cleared (or if TE is never set).
This bit enables the receiver. It is set and cleared by software.
0: Receiver is disabled
1: Receiver is enabled and begins searching for a start bit
Note: Before selecting Mute mode (setting the RWU bit), the SCI must first receive
some data, otherwise it cannot function in Mute mode with wakeup by Idle line
detection.
This bit determines if the SCI is in mute mode or not. It is set and cleared by
software and can be cleared by hardware when a wakeup sequence is recognized.
0: Receiver in Active mode
1: Receiver in Mute mode
This bit set is used to send break characters. It is set and cleared by software.
0: No break character is transmitted.
1: Break characters are transmitted.
Note: If the SBK bit is set to ‘1’ and then to ‘0’, the transmitter will send a Break word
at the end of the current word.
6
Figure
57). The RDR register provides the parallel interface between the
DR5
R/W
5
DR4
R/W
4
Figure
Function
DR3
R/W
3
57).
DR2
R/W
2
Reset value: undefined
DR1
R/W
1
ST72324Bxx
DR0
R/W
0