ST72324BJ6 STMicroelectronics, ST72324BJ6 Datasheet - Page 21

• Manufacturer Part Number: ST72324BJ6
• Description: 5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324BJ6

• Hdflash Endurance: 1 kcycle at 55 °C, data retention 40 years at 85 °C
• Clock Sources: crystal/ceramic resonator oscillators, int. RC osc. and ext. clock input
• 4 Power Saving Modes: Slow, Wait, Active-halt, and Halt

ST72324Bxx
Table 3.
Address
002Eh to
0012h to
002Ah
002Bh
002Ch
002Dh
003Ah
003Bh
003Ch
003Dh
003Eh
000Fh
0010h
0011h
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Fh
0040h
Watchdog WDGCR
Port F
Timer A
Hardware register map (continued)
Block
Flash
MCC
SPI
ITC
SI
(1)
PFDR
PFDDR
PFOR
SPIDR
SPICR
SPICSR
ISPR0
ISPR1
ISPR2
ISPR3
EICR
FCSR
SICSR
MCCSR
MCCBCR
TACR2
TACR1
TACSR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
TACLR
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
Register label
Port F data register
Port F data direction register
Port F option register
SPI data I/O register
SPI control register
SPI control/status register
Interrupt software priority register 0
Interrupt software priority register 1
Interrupt software priority register 2
Interrupt software priority register 3
External interrupt control register
Flash control/status register
Watchdog control register
System integrity control/status register
Main clock control/status register
Main clock controller: beep control register
Timer A control register 2
Timer A control register 1
Timer A control/status register
Timer A input capture 1 high register
Timer A input capture 1 low register
Timer A output compare 1 high register
Timer A output compare 1 low register
Timer A counter high register
Timer A counter low register
Timer A alternate counter high register
Timer A alternate counter low register
Timer A input capture 2 high register
Timer A input capture 2 low register
Timer A output compare 2 high register
Timer A output compare 2 low register
Reserved area (15 bytes)
Reserved area (3 bytes)
Reserved area (1 byte)
Register name
Register and memory map
Reset status
000x 000xb
xxxx x0xxb
00h
FCh
FCh
FFh
FFh
FFh
FFh
00h
7Fh
FFh
FFh
00h
00h
0xh
00h
00h
00h
00h
00h
00h
80h
00h
80h
00h
xxh
xxh
xxh
xxh
xxh
(2)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read only
Read only
R/W
R/W
Read only
Read only
Read only
Read only
Read only
Read only
R/W
R/W
R/W
Remarks
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