ST7263BK1 STMicroelectronics, ST7263BK1 Datasheet - Page 119

• Manufacturer Part Number: ST7263BK1
• Description: LOW SPEED USB 8-BIT MCU FAMILY WITH UP TO 32K FLASH/ROM, DFU CAPABILITY, 8-BIT ADC, WDG, TIMER, SCI and I2C
• Manufacturer: STMicroelectronics

Specifications of ST7263BK1

• 4, 8, 16 Or 32 Kbytes Program Memory: high density Flash (HDFlash), FastROM or ROM with Read-Out and Write protection

ST7263Bxx
I²C Status register 1 (SR1)
Reset value: 0000 0000 (00h)
EVF
7
7 EVF Event flag
6 Reserved. Forced to 0 by hardware.
5 TRA Transmitter/Receiver.
4 BUSY Bus busy.
This bit is set by hardware as soon as an event occurs. It is cleared by software
reading SR2 register in case of error event or as described in
cleared by hardware when the interface is disabled (PE=0).
0: No event
1: One of the following events has occurred:
●
●
●
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When BTF is set, TRA=1 if a data byte has been transmitted. It is cleared
automatically when BTF is cleared. It is also cleared by hardware after detection of
Stop condition (STOPF=1), loss of bus arbitration (ARLO=1) or when the interface
is disabled (PE=0).
0: Data byte received (if BTF=1)
1: Data byte transmitted
This bit is set by hardware on detection of a Start condition and cleared by
hardware on detection of a Stop condition. It indicates a communication in progress
on the bus. The BUSY flag of the I2CSR1 register is cleared if a Bus Error occurs.
0: No communication on the bus
1: Communication ongoing on the bus
Note: The BUSY flag is NOT updated when the interface is disabled (PE=0). This
0
BTF=1 (Byte received or transmitted)
ADSL=1 (Address matched in Slave mode while ACK=1)
SB=1 (Start condition generated in Master mode)
AF=1 (No acknowledge received after byte transmission)
STOPF=1 (Stop condition detected in Slave mode)
ARLO=1 (Arbitration lost in Master mode)
BERR=1 (Bus error, misplaced Start or Stop condition detected)
Address byte successfully transmitted in Master mode.
can have consequences when operating in Multimaster mode; i.e. a second
active I
a conflict resulting in lost data. A software workaround consists of checking
that the I
TRA
2
C master commencing a transfer with an unset BUSY bit can cause
Doc ID 7516 Rev 8
2
C is not busy before enabling the I
BUSY
Read only
BTF
ADSL
2
C Multimaster cell.
On-chip peripherals
Figure
M/SL
48. It is also
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SB
0