ST7263BK1 STMicroelectronics, ST7263BK1 Datasheet - Page 84

• Manufacturer Part Number: ST7263BK1
• Description: LOW SPEED USB 8-BIT MCU FAMILY WITH UP TO 32K FLASH/ROM, DFU CAPABILITY, 8-BIT ADC, WDG, TIMER, SCI and I2C
• Manufacturer: STMicroelectronics

Specifications of ST7263BK1

• 4, 8, 16 Or 32 Kbytes Program Memory: high density Flash (HDFlash), FastROM or ROM with Read-Out and Write protection

On-chip peripherals
Note:
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As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing this
bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the
recognition of the start bit of the next frame.
Idle characters
Setting the TE bit drives the SCI to send an idle frame before the first data frame.
Clearing and then setting the TE bit during a transmission sends an idle frame after the
current word.
Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit is set i.e. before writing the next byte in
the SCIDR.
Receiver
The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9
bits and the MSB is stored in the R8 bit in the SCICR1 register.
Character reception
During a SCI reception, data shifts in least significant bit first through the RDI pin. In this
mode, the SCIDR register consists or a buffer (RDR) between the internal bus and the
received shift register (see
Procedure
1.
2.
3.
When a character is received:
●
●
●
Clearing the RDRF bit is performed by the following software sequence done by:
1.
2.
The RDRF bit must be cleared before the end of the reception of the next character to avoid
an overrun error.
Break character
When a break character is received, the SCI handles it as a framing error.
Idle character
When a idle frame is detected, there is the same procedure as a data received character
plus an interrupt if the ILIE bit is set and the I bit is cleared in the CC register.
Overrun error
An overrun error occurs when a character is received when RDRF has not been reset. Data
can not be transferred from the shift register to the RDR register as long as the RDRF bit is
not cleared.
Select the M bit to define the word length.
Select the desired baud rate using the SCIBRR and the SCIERPR registers.
Set the RE bit, this enables the receiver which begins searching for a start bit.
The RDRF bit is set. It indicates that the content of the shift register is transferred to the
RDR.
An interrupt is generated if the RIE bit is set and the I bit is cleared in the CC register.
The error flags can be set if a frame error, noise or an overrun error has been detected
during reception.
An access to the SCISR register
A read to the SCIDR register.
Figure
Doc ID 7516 Rev 8
41).
ST7263Bxx